AT49BV6416 Datasheet, PDF (1/30 Pages) ATMEL Corporation – 64-megabit (4M x 16) Page Mode 2.7-volt Flash Memory

Features
• 64-megabit (4M x 16) Flash Memory
• 2.7V - 3.6V Read/Write
• High Performance
– Asynchronous Access Time – 70 ns
– Page Mode Read Time – 20 ns
• Sector Erase Architecture
– Eight 4K Word Sectors with Individual Write Lockout
– One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout
• Typical Sector Erase Time: 32K Word Sectors – 700 ms; 4K Word Sectors – 200 ms
• Four Plane Organization, Permitting Concurrent Read in Any of Three Planes not Being
Programmed/Erased
– Memory Plane A: 16M of Memory Including Eight 4K Word Sectors
– Memory Plane B: 16M of Memory Consisting of 32K Word Sectors
– Memory Plane C: 16M of Memory Consisting of 32K Word Sectors
– Memory Plane D: 16M of Memory Consisting of 32K Word Sectors
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation
– 30 mA Active
– 35 µA Standby
• 2.2V I/O Option Reduces Overall System Power
• Data Polling and Toggle Bit for End of Program Detection
• VPP Pin for Write Protection and Accelerated Program Operations
• RESET Input for Device Initialization
• TSOP Package
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Common Flash Interface (CFI)
• Green (Pb/Halide-free) Packaging Option
64-megabit
(4M x 16)
Page Mode
2.7-volt Flash
Memory
AT49BV6416
AT49BV6416T
1. Description
The AT49BV6416(T) is a 2.7-volt 64-megabit Flash memory. The memory is divided
into multiple sectors and planes for erase operations. The device can be read or
reprogrammed off a single 2.7V power supply, making it ideally suited for in-system
programming. The output voltage can be separately controlled down to 2.2V through
the VCCQ supply pin. The device can operate in the asynchronous or page read
mode.
The AT49BV6416(T) is divided into four memory planes. A read operation can occur
in any of the three planes which is not being programmed or erased. This concurrent
operation allows improved system performance by not requiring the system to wait for
a program or erase operation to complete before a read is performed. To further
increase the flexibility of the device, it contains an Erase Suspend and Program Sus-
pend feature. This feature will put the erase or program on hold for any amount of time
and let the user read data from or program data to any of the remaining sectors. There
is no reason to suspend the erase or program operation if the data to be read is in
another memory plane. The end of program or erase is detected by Data Polling or
toggle bit.
3451C–FLASH–2/05