AT49BV040B Datasheet, PDF (1/21 Pages) ATMEL Corporation – 4-megabit (512K x 8) Flash Memory

Features
• Single Supply for Read and Write: 2.7V to 5.5V
• Fast Read Access Time – 70 ns (V_CC = 2.7V to 3.6V); 55 ns (V_CC = 4.5V to 5.5V)
• Internal Program Control and Timer
• Flexible Sector Architecture
– One 16K Bytes Boot Sector with Programming Lockout
– Two 8K Bytes Parameter Sectors
– Eight Main Memory Sectors (One 32K Bytes, Seven 64K Bytes)
• Fast Erase Cycle Time – 8 Seconds
• Byte-by-Byte Programming – 10 µs/Byte Typical
• Hardware Data Protection
• DATA Polling or Toggle Bit for End of Program Detection
• Low Power Dissipation
– 20 mA Active Current
– 25 µA CMOS Standby Current for V_CC = 2.7V to 3.6V
– 30 µA CMOS Standby Current for V_CC = 4.5V to 5.5V
• Minimum 100,000 Write Cycles
4-megabit
(512K x 8)
Flash Memory
AT49BV040B
1. Description
The AT49BV040B is a 2.7V to 5.5V in-system reprogrammable Flash Memory. Its
4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers an access time of
70 ns (V_CC = 2.7V to 3.6V) and an access time of 55 ns (V_CC = 4.5V to 5.5V). The
power dissipation over the industrial temperature range with V_CC = 2.7V to 3.6V is 72
mW and is 110 mW with V_CC = 4.5V to 5.5V.
When the device is deselected, the CMOS standby current is less than 30 µA. To
allow for simple in-system reprogrammability, the AT49BV040B does not require high
input voltages for programming. Reading data out of the device is similar to reading
from an EPROM; it has standard CE, OE, and WE inputs to avoid bus contention.
Reprogramming the AT49BV040B is performed by erasing a sector of data and then
programming on a byte by byte basis. The byte programming time is a fast 10 µs. The
end of a program or erase cycle can be optionally detected by the DATA polling or
toggle bit feature. Once the end of a byte program cycle has been detected, a new
access for a read or program can begin. The typical number of program and erase
cycles is in excess of 100,000 cycles.
The device is erased by executing a chip erase or a sector erase command sequence;
the device internally controls the erase operations. The memory array of the
AT49BV040B is organized into two 8K byte parameter sectors, eight main memory
sectors, and one boot sector.
The device has the capability to protect the data in the boot sector; this feature is
enabled by a command sequence. The 16K-byte boot sector includes a reprogram-
ming lock out feature to provide data integrity. The boot sector is designed to contain
user secure code, and when the feature is enabled, the boot sector is permanently
protected from being reprogrammed.
3499B–FLASH–4/06