AT45DB321C_14 Datasheet, PDF (1/40 Pages) ATMEL Corporation – Automated Erase Operations

Features
• Single 2.7 - 3.6V Supply
• RapidS^™ Serial Interface: 40 MHz Maximum Clock Frequency
(SPI Modes 0 and 3 Compatible for Frequencies Up to 33 MHz)
• Page Program
– 8192 Pages (528 Bytes/Page)
• Automated Erase Operations
– Page Erase 528 Bytes
– Block Erase 4,224 Bytes
• Two 528-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming the Flash Array
• Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
• Low-power Dissipation
– 10 mA Active Read Current Typical
– 6 µA Standby Current Typical
• Hardware and Software Data Protection Features
– Individual Sector Locking
• Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
• JEDEC Standard Manufacturer and Device ID Read
• 100,000 Program/Erase Cycles per Page Minimum
• Data Retention – 20 years
• Commercial and Industrial Temperature Ranges
• Green (Pb/Halide-free/RoHS Compliant) Packaging Options
32-megabit
2.7 volt
DataFlash^®
AT45DB321C
For New
Designs Use
AT45DB321D
1. Description
The AT45DB321C is an SPI compatible, serial-interface Flash memory ideally suited
for a wide variety of digital voice-, image-, program code- and data-
storage applications. The AT45DB321C supports a 4-wire serial interface known as
RapidS for applications requiring very high speed operations.
Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. In
addition to the 33-megabit main memory, the AT45DB321C also contains two SRAM
buffers of 528 bytes each.
The buffers allow the receiving of data while a page in the main page Memory is being
reprogrammed, as well as writing a continuous data stream. EEPROM emulation (bit
or byte alterability) is easily handled with a self-contained three step read-modify-write
operation. Unlike conventional Flash memories that are accessed randomly with mul-
tiple address lines and a parallel interface, the DataFlash uses a RapidS serial
interface to sequentially access its data. The simple sequential access dramatically
reduces active pin count, facilitates hardware layout, increases system reliability, min-
imizes switching noise, and reduces package size. The device is optimized for use in
many commercial and industrial applications where high-density, low-pin count, low-
voltage and low-power are essential. The device operates at clock frequencies up to
40 MHz with a typical active read current consumption of 10 mA.
3387M–DFLASH–2/08