AT28HC256_08 Datasheet, PDF (1/16 Pages) ATMEL Corporation – 256 (32K x 8) High Speed Parallel Parallel

Features
• Fast Read Access Time - 70 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
• Fast Write Cycle Times
– Page Write Cycle Time: 3 ms or 10 ms Maximum
– 1 to 64-Byte Page Write Operation
• Low Power Dissipation
– 80 mA Active Current
– 3 mA Standby Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 10⁴ or 10⁵ Cycles
– Data Retention: 10 Years
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-Wide Pinout
• Full Military, Commercial, and Industrial Temperature Ranges
Description
The AT28HC256 is a high-performance Electrically Erasable and Programmable
Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Man-
ufactured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256
Pin Configurations
TSOP
(continued)
Pin Name
Function
Top View
A0 - A14
CE
OE
WE
I/O0 - I/O7
NC
DC
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
Don’t Connect
OE 1
A11 2
A9 3
A8 4
A13 5
WE 6
VCC 7
A14 8
A12 9
A7 10
A6 11
A5 12
A4 13
A3 14
28 A10
27 CE
26 I/O7
25 I/O6
24 I/O5
23 I/O4
22 I/O3
21 GND
20 I/O2
19 I/O1
18 I/O0
17 A0
16 A1
15 A2
LCC, PLCC
Top View
CERDIP, PDIP, FLATPACK
Top View
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
NC 12
I/O0 13
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
Note: PLCC package pins 1 and
17 are DON’T CONNECT.
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O0 11
I/O1 12
I/O2 13
GND 14
28 VCC
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
PGA
Top View
256 (32K x 8)
High Speed
Parallel
EEPROMs
AT28HC256
Rev. 0007G–10/98
1