AT28HC256N_14 Datasheet, PDF (1/13 Pages) ATMEL Corporation – Automatic Page Write Operation

Features
• Fast Read Access Time – 90 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
• Fast Write Cycle Times
– Page Write Cycle Time: 3 ms Maximum
– 1 to 64-byte Page Write Operation
• Low Power Dissipation: 300 µA Standby Current (CMOS)
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 10⁵ Cycles
– Data Retention: 10 Years
• Single 5V ±10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-wide Pinout
Description
The AT28HC256N is a high-performance electrically erasable and programmable read
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256N offers
access times to 90 ns with power dissipation of just 440 mW. When the AT28HC256N
is deselected, the standby current is less than 3 mA.
The AT28HC256N is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64
bytes of data are internally latched, freeing the addresses and data bus for other oper-
ations. Following the initiation of a write cycle, the device will automatically write the
latched data using an internal control timer. The end of a write cycle can be detected
by DATA Polling of I/O₇. Once the end of a write cycle has been detected a new
access for a read or write can begin.
Atmel’s AT28HC256N has additional features to ensure high quality and manufactura-
bility. The device utilizes internal error correction for extended endurance and
improved data retention characteristics. An optional software data protection mecha-
nism is available to guard against inadvertent writes. The device also includes an extra
64 bytes of EEPROM for device identification or tracking.
Pin Configurations
Pin Name
A0 - A14
CE
OE
WE
I/O0 - I/O7
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
LCC, PLCC
Top View
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
NC 12
I/O0 13
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
256 (32K x 8)
High-speed
Parallel
EEPROM
AT28HC256N
3446B–PEEPR–4/04