AX88871AP Datasheet, PDF (9/30 Pages) ASIX Electronics Corporation – 10/100BASE Dual Speed Bripeater Controller

AX88871AP Bripeater
2.0 Pin Description
The following terms describe the AX88871A pinout:
All pin names with the “/” suffix are asserted low.
I
=
Input
O
=
Output
I/O
=
Input /Output
2.1 MII interfaces
Signal Name
TXER[7:0]
or
COL[7:0]
TXD[7:0][3:0]
TXEN[7:0]
RXD[7:0][3:0]
RXER[7:0]
RXCLK[7:0]
RXDV[7:0]
CRS[7:0]
COL_O[6]
COL_O[7]
Type
O
or
I
O
O
I
I
I
I
I
O
O
Pin No.
Description
89, 72, 56 Transmit Error : When /HALF10 pin set to “high”. TXER is transition
40, 24, 9 synchronously with respect to the rising edge of TXCLK . Asserted
202, 187 high when a code violation is request to be send
Collision : When /HALF10 pin set to “low”. COL is input from PHY,
when 10Mbps PHY is in half-duplex mode.
88-85, 70-67 Transmit Data : TXD[3:0] is transition synchronously with respect to
55-52, 39-36 the rising edge of TXCLK. For each TXCLK period in which TXEN is
23-20, 8-5 asserted, TXD[3:0] are accepted for transmission by the PHY.
201-198
186-185
182-181
84, 66,51 Transmit Enable : TXEN is transition synchronously with respect to the
35, 19, 4 rising edge of TXCLK. TXEN indicates that the port is presenting
197, 180 nibbles on TXD [3:0] for transmission.
83-80, 65-62 Receive Data : RXD [3:0] is driven by the PHY synchronously with
49-46, 34-31 respect to RXCLK.
18-15, 3-2
208-207
195-192
179-176
74, 57, 42 Receive Error : RXER ,is driven by PHY and synchronous to RXCLK,
27, 11, 203, is asserted for one or more RXCLK periods to indicate to the port that
188, 172 an error has detected.
79, 61, 45 Receive Clock : RX_CLK is a continuous clock that provides the
30, 14, 206, timing reference for the transfer of the RXDV,RXD [3:0] and RXER
191, 175 signals from the PHY to the MII port of the repeater.
75, 58, 43 Receive Data Valid : RX_DV is driven by the PHY synchronously with
28, 12, 204, respect to RXCLK. Asserted high when valid data is present on RXD
189, 173 [3:0].
76, 59, 44, 29, Carrier Sense : Asynchronous signal CRS is asserted by the PHY when
13, 205, 190, receive medium is non-idle at full duplex mode.
174
73
Collision : Collision detection signal for port 6
90
Collision : Collision detection signal for port 7
9
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