AX88141 Datasheet, PDF (19/44 Pages) ASIX Electronics Corporation – 100BASE-TX/FX PCI BUS FAST ETHERNET MAC CONTROLLER WITH POWER MANAGEMENT

AX88141
CONFIDENTIAL
PRELIMINARY
4.2 Host REGs
4.2.1 Bus Mode Register (REG0)
FIELD
31:22
21
20
19:14
13:8
7
6:2
1
0
R/W/C
-
R/W
R/W
-
R/W
R/W
-
R/W
R/W
DESCRIPTION
RESERVED
RML - Read Multiple
When set, the AX88141 supports the memory-read-multiple command on the PCI bus. This bus command is used in
memory read bursts with more than one longword. When reset, the AX88141 uses memory-read command in all its
memory read accesses on the PCI bus.
DBO - Descriptor Byte Ordering Mode
When set, the AX88141 operates in big edian ordering mode for descriptors only.
When reset, the AX88141 operates in little endian mode.
Reserved.--Written as “0” for future compatibility concern.
PBL - Programmable Burst Length
Indicates the maximum number of longwords to be transfered in one DMA transaction. If reset, the AX88141 burst is
limited only by the amount of data stored in the receive FIFO (at least 16 longword), or by the amount of free space in
the transmit FIFO (at least 16 longword) before issuing a bus request. The PBL can be programmed with permissible
values 0,1,2,4,8,16, or 32. After reset, the PBL default value is 0.
BLE - Big/Little Endian
When set, the AX88141 operates in big endian byte ordering mode. When reset, the AX88141 operates in little endian
byte ordering mode. Big endian is applicable only for data buffer
RESERVED
BAR - Bus Arbitration
Selects the internal bus arbitration between the receive and transmit processes.
When set, a round robin arbitration scheme is applied resulting in equal sharing between processes. When reset, the
receive process has priority over the transmit process, unless the AX88141 is currently transmitting.
SWR - Software Reset
When set, the AX88141 resets all internal hardware with the exception of the configuration area and also, it does not
change the port select setting (REG6<18>).
Software reset does not affect the configuration area.
Tab - 19 REG0 Bus Mode Register Description
4.2.2 Magic Packet Password Low (REG0B)
FIELD
31:0
R/W
DESCRIPTION
R/W MPPL - Magic Packet Password Low
This register contains the magic packet password bits 31 to 0.
Tab - 20 REG1 Transmit Poll Demand Register Description
4.2.3 Transmit Poll Demand (REG1)
FIELD
31:0
R/W
W
DESCRIPTION
TPD - Transmit Poll Demand
When written with any value, the AX88141 checks for frames to be transmitted. If no descriptor is available, the transmit
process returns to the suspended states and REG5<2> is asserted. If the descriptor is available the transmit process resumes.
Tab - 21 REG1 Transmit Poll Demand Register Description
4.2.4 Magic Packet Password High (REG1B)
FIELD
31:16
15:0
R/W
R
R/W
DESCRIPTION
Reserved
MPPH - Magic Packet Password High
This register contains the magic packet password bits 47 to 32.
Tab - 22 REG1 Transmit Poll Demand Register Description
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