AX88140A Datasheet, PDF (14/46 Pages) ASIX Electronics Corporation – Fast Ethernet MAC Controller

AX88140A
PRELIMINARY
2.3 Boot ROM , Serial ROM , General-purpose signals group
SIGNAL
BR_A<0>
BR_A<1>
BR_AD<7>
BR_AD<6>
BR_AD<5>
BR_AD<4>
BR_AD<3>
BR_AD<2>
BR_AD<1>
BR_AD<0>
BR_CE#
SR_CK
SR_CS
SR_DI
SR_DO
GENP<7>
GENP<6>
GENP<5>
GENP<4>
GENP<3>
GENP<2>
GENP<1>
GENP<0>
TYPE
PIN
PIN
DESCRIPTION
NUMBER NUMBER
FOR 160 PIN FOR 144 PIN
0
112
0
113
I/O
110,
109,
106,
105,
104,
103,
102,
101
102
Boot ROM address line bit 0.
103
Boot ROM address line bit 1. This pin also latches the boot ROM
address and control lines by the two external latches.
100,
Boot ROM address and data multiplexed lines bits 7 through 0. In
99,
the first of two consecutive address cycles, these lines contain the
96,
boot ROM address bits 9 through 2; followed by boot ROM
95,
address bits 17 through 10 in the second cycle. During the data
94,
cycle, bits 7 through 0 contain data.
93,
92,
91
O
111
101
Boot ROM chip enable.
O
88
78
Serial ROM clock signal.
O
89
O
87
79
Serial ROM chip-select signal.
77
Serial ROM data-in signal.
I
86
76
Serial ROM data-out signal.
I/O
99,
98,
97,
96,
93,
92,
91,
90
89,
General-purpose pins can be used by software as either status pins
88,
or control pins. These pins can be configured by software to
87,
perform either input or output functions.
86,
83,
82,
81,
80
Tab - 2 Boot ROM , Serial ROM , General-purpose signals group
2.4 MII/SYM/SRL interface signals group
SIGNAL
MCOL
MCRS
MRXDV
MRXERR
MDC
MDIO
MII/SRL
TYPE PIN
PIN
DESCRIPTION
NUMBER
NUMBER
FOR 160 PIN FOR 144 PIN
I
126
I
127
I
125
I
124
O
116
I/O
115
O
147
112
Collision detected is asserted when detected by an
external physical layer protocol(PHY) device.
113
Carrier sense is asserted by the PHY when the media
is active.
111
Data valid is asserted by an external PHY when
receive data is present on the MRXD/SYRXD lines
and is deasserted at the end of the packet. This signal
should be synchronized with the
MRCLK/SYMRCLK signal.
110
Receive error asserts when a data decoding error is
detected by an external PHY device. This signal is
synchronized to MRCLK/SYMRCLK and can be
asserted for a minimum of one receive clock. When
asserted during a packet reception, it sets the cyclic
redundancy check(CRC) error bit in the receive
descriptor (RDESO).
106
MII management data clock is sourced by the
AX88140A to the PHY devices as a timing reference
for the transfer of information on the MII_MDIO
signal.
105
MII management data input/output transfers control
information and status between the PHY and the
AX88140A.
133
Indicates the selected port: SRL or MII/SYM. When
asserted, the MII/SYM port is active. When
deasserted, the SRL port is active.
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ASIX ELECTRONICS CORPORATION