AX88190AL Datasheet, PDF (10/49 Pages) ASIX Electronics Corporation – 10/100BASE PCMCIA Fast Ethernet MAC Controller

AX88190A
GPIO3#
GPIO2
GPIO1#
GPIO0#
I/O
41
I/O
42
I/O
43
I/O
45
Tab - 6 General Pursose I/O pins group
PCMCIA Fast Ethernet MAC Controller
Default “1”. The pin reflects register offset 1Ah bit 3 inverted value.
Default “0”. The pin reflects register offset 1Ah bit 2 value.
Default “1”. The pin reflects register offset 1Ah bit 1 inverted value.
Default “1”. The pin reflects register offset 1Ah bit 0 inverted value.
2.7 Miscellaneous pins group
SIGNAL
LCLK/XTALIN
XTALOUT
CLKO
CLK_DIV3#
PPWDN
RESET
TEST#
EEPROM SIZE
NC
LVDD
HVDD
VSS
TYPE
I
O
O
I/PU
O
I/PD
I/PU
I/PU
N/A
P
P
P
PIN NO.
DESCRIPTION
103 CMOS Local Clock : Typical a 25Mhz clock, +/- 100 ppm, 40%-60%
duty cycle. ( See application note also )
Crystal Oscillator Input : Typical a 25Mhz crystal, +/- 25 ppm can be
connected across XTALIN and XTALOUT.
104 Crystal Oscillator Output : Typical a 25Mhz crystal, +/- 25 ppm can be
connected across XTALIN and XTALOUT. If a single-ended external
clock (LCLK) is connected to XTALIN, the crystal output pin should
be left floating.
101 Clock Output : This clock is source from LCLK/XTALIN.
67 Clock Devide 3 Enable : Active low to enable the devided 3 circuit.
That internally devides LCLK/XTALIN input frequeny by 3 and then
feed into internal circuit for system clock used.
Default value set to logic high, this function is disabled.
114 Phy Power Down : This pin connects to PHY chip power down mode
control input.
127 Reset
Reset is active high then place AX88190A into reset mode
immediately. During Falling edge the AX88190A loads the EEPROM
data.
77
Test Pin : Active LOW
The pin is just for test mode setting purpose only. Must be pull high
when normal operation.
73
EEPROM SIZE = 0 : 93C46 128 byte type EEPROM is used.
EEPROM SIZE = 1 : 93C56 256 byte type EEPROM is used.
46–48, 50– No Connection : for manufacturing test only.
53, 55-56,
44, 54, Power Supply : +3.3V DC.
100, 110,
126, 128
19, 29, 64, Power Supply : +5V DC.
75
Note : for pure 3.3V single power solution, all the HVDD pin can
connect to +3.3V. Care should be taken that HVDD input power must
be greater or equal ( > = ) than LVDD.
11, 24, 34, Power Supply : +0V DC or Ground Power.
39, 40, 49,
59, 69, 81,
93, 102, 105,
119
Tab - 7 Miscellaneous pins group
10
ASIX ELECTRONICS CORPORATION