DLVR-L02D-E2NJ-C-NI5F Datasheet, PDF (10/18 Pages) All Sensors Corporation – DLVR Series Low Voltage Digital Pressure Sensors

SPI Interface
SPI Command Sequence
DLVR sensors using the SPI interface option provide 3 signals for communication: SCLK, SS (Slave Select), and MISO.
This read-only signaling uses a hardware protocol to control the sensor, differing slightly with the speed/power option
selected as described below:
Fast(F), Noise Reduced(N) and Low-Power(L) Configurations: After power-up, the part enters Free Running
mode and begins its periodic conversion cycle, at the interval determined by the programmed Power/Speed
option. This is the simplest configuration. The only bus interaction with the host is the SPI DataRead opera-
tions. Polling the sensor at a rate slower than the internal update rate will minimize bus activity and ensure
that new values are presented with each transfer. Note that the Status bits should still be checked to verify
updated data and the absence of error conditions.
Sleep(S) Configuration: As with the I2C option, the part enters Triggered mode after power-up, and waits for
a command from the bus master. To wake the part and start a measurement cycle, the SS pin must be driven
low by the host for at least 8usec, then driven high. This can be done by shifting a dummy byte of 8 bits from
the sensor. This bus activity can be considered the SPI StartAll command, where the rising edge of SS is the
required input to start conversion. Updated conversion data is written to the output registers after a period
dependent on configuration options ( see Performance Characteristics). After this update of the registers, the
core goes to an inactive (sleep) state. The DataRead command simply consists of shifting out 2, 3, or 4 bytes
of data from the sensor. The host can check the Status bits of the output to verify that new data has been
provided. The part remains inactive following this read operation, and another StartAll operation is needed to
wake the part when the next conversion is to be performed.
SPI Bit Pattern
The sequence of bits and bus signals are shown in the following illustration (Figure 4). Refer to Figure 5 in the Interface
Timing Diagram section for detailed timing data. As previously described, the incoming data may be terminated by rais-
ing SS after 2, 3, or 4 bytes have been received as illustrated below.
Figure 4 - SPI Bit Pattern
Page 10