ALN1751T2_17 Datasheet, PDF (2/2 Pages) Advanced Semiconductor Business Inc. – Internally Matched LNA Module

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Application Circuit
C1
IN
plerow^TM ALN1751T2
Internally Matched LNA Module
VS
+-
Tantal or MLC (Multi Layer Ceramic)
Capacitor
C2
ALN
OUT
1) The tantal or MLC (Multi Layer Ceramic) capacitor is optional and for bypassing the AC noise introduced
from the DC supply. The capacitance value may be determined by customer’s DC supply status. The ca-
pacitor should be placed as close as possible to Vs pin and be connected directly to the ground plane for
the best electrical performance.
2) DC blocking capacitors are always necessarily placed at the input and output port for allowing only the
RF signal to pass and blocking the DC component in the signal. The DC blocking capacitors are includ-
ed inside the ALN module. Therefore, C1 & C2 capacitors may not be necessary, but can be added just
in case that the customer wants. The value of C1 & C2 is determined by considering the application fre-
quency.
Recommended Soldering Reflow Process
260 C
20~40 sec
Evaluation Board Layout
Vs
Ramp-up
(3 C/sec)
IN
OUT
Ramp-down
200 C
(6 C/sec)
150 C
60~180 sec
Size 25x25 mm
(for ALN-AT, BT, WT, T Series – 10x10 mm)
Copyright 2009-2017 ASB Inc. All rights reserved. Datasheet subject to change without notice. ASB assumes no re-
sponsibility for any errors which may appear in this datasheet. No part of the datasheet may be copied or reproduced
in any form or by any means without the prior written consent of ASB.
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www.asb.co.kr
August 2017