APL1705 Datasheet, PDF (1/1 Pages) Advanced Semiconductor Business Inc. – PLL Module

Features
· +4 dBm Output Level at 1705 MHz
· Channel Step Size : 100 kHz
· 2^nd Harmonic : < -20 dBc
· Spurious Level : < -70 dBc
· Lock Time : < 10 ms
· 20 mA Current Consumption
Description
The plerow^TM PLL synthesizer module was
designed for use in wireless and wireline
systems in a wide range of frequency from
50 MHz to 6 GHz. ASB’s PLL provides
exceptionally low spurious and phase noise
performance with fast locking time and low
current consumption. All products are
available in a surface-mount type package.
Specifications
Parameter
Frequency Range
Output Power
Supply Voltage
Current Consumption
Channel Step Size
2^nd Harmonics
Spurious Level
Lock Time
Reference Frequency
Reference Input Level
Phase Noise (C / N)
@ 10 kHz
@ 100 kHz
Output Impedance
Operating Temp. Range
Package Type & Size
Unit
MHz
dBm
V
mA
kHz
dBc
dBc
ms
MHz
dBm
dBc/Hz
dBc/Hz
Ω
°C
mm
Min.
1685
3
4.7
-5
Typical
1705
4
5.0
23
100
-25
-78
3
10
0
Max.
1725
5
5.3
30
-20
-70
10
5
-106
-103
-100
-122
-119
-116
50
-40
25
85
SMT, 19.0W×19.0L×5.8H
1) Measurement conditions are as follows: T = 25°C, VCC = 5 V, Freq. = 1705 MHz, 50 ohm system.
Plerow APL1705
PLL Module
More Information
Website: www.asb.co.kr
E-mail: [e-mail]
Tel: [phone]
Fax: [phone]
ASB, Inc., 4^th Fl. Venture Town
Bldg, KT HRDC, 367-17
Goijeong-Dong, Seo-Gu,
Daejeon, 302-716, Korea
Outline Drawing
Top View
A
C
B
Side View
1/1
Bottom View
D
E
F
I
H
G
Pin Configuration
1
CLOCK
2
DATA
3
ENABLE
4
OSC IN
9
VCC (VCO)
13
RF OUT
15
VCP (PLL)
16 LOCK DETECT
Others
Ground
Dimension (mm)
A
19.0
B
19.0
C
5.8
D
1.5
E
0.5
F
1.75
G
1.35
H
15.0
I
0.9
Tolerance: ± 0.2
www.asb.co.kr
March 2004