APL1705-RT Datasheet, PDF (1/1 Pages) Advanced Semiconductor Business Inc. – PLL Module

plerow^TM APL1705-R/T
PLL Module
Features
· +4 dBm Output Level at 1705 MHz
· 2^nd Harmonic : < -20 dBc
· Spurious Level : < -70 dBc
· Lock Time : < 10ms
· 30 mA Current Consumption
· Strip-line Resonator
Description
The plerow^TM PLL synthesizer module was
designed for use in wireless and wireline
systems in a wide range of frequency from
50 MHz to 6 GHz. ASB’s PLL provides ex-
ceptionally low spurious and phase noise
performance with fast locking time and low
current consumption. All products are avail-
able in a surface-mount type package.
Specifications
Parameter
Unit
Min.
Typical
Max.
Frequency Range
MHz
1705
Output Power
dBm
+2
+4
+6
Supply Voltage
V
4.7
5.0
5.3
Current Consumption
mA
26
30
Channel Step Size
kHz
2^nd Harmonics
dBc
-
-30
-20
Spurious Level
dBc
-70
Lock Time
ms
3
10
Reference Frequency
MHz
-
Reference Input Level
dBm
-
Phase Noise
(C / N)
@ 1 kHz
@ 10 kHz
@ 100 kHz
dBc/Hz
-80
-105
-120
-75
-100
-115
Output Impedance
Ω
50
Operating Temp. Range
°C
-40
+25
+85
Package Type & Size
mm
SMT, 19.0W×19.0L×5.8H
1) Measurement conditions are as follows: T = 25°C, V_CC =5.0 V, Freq. = 1705 MHz, 50 ohm system.
More Information
Website: www.asb.co.kr
E-mail: [e-mail]
Tel: [phone]
Fax: [phone]
ASB Inc., 4th Fl. Venture Town
Bldg., 367-17 Goijeong-Dong,
Seo-Gu, Daejon 302-716, Korea
Outline Drawing
Top View
A
C
B
Side View
Bottom View
D
E
F
I
H
G
Pin Configuration
1
Ground
2
Ground
3
Ground
4
Ground
9
VCC (VCO)
13
RF OUT
15
VCP (PLL)
16 LOCK DETECT
Others
Ground
Dimension (mm)
A
19.0
B
19.0
C
5.8
D
1.5
E
0.5
F
1.75
G
1.35
H
15.0
I
0.9
Tolerance: ± 0.2
1/1
www.asb.co.kr
6/1/2006