SA56 Datasheet, PDF (5/7 Pages) Cirrus Logic – PULSE WIDTH MODULATION AMPLIFIER

OPERATING
CONSIDERATIONS
SA56
GENERAL
7
TLIM
Temperature limit, CMOS. This pin can
Please read Application Note 1 "General Operating Consid-
erations" which covers stability, power supplies, heat sinking,
mounting, and specification interpretation. Visit www.apexmi-
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GROUND PINS
be used as a flag for an over temperature
condition. Under normal operation this
pin will be logic low. When junction tem-
perature exceeds approximately 160°C
this pin will change to logic high and
the output will be latched off. Ground-
ing this pin disables over temperature
protection. This pin should be left open
if over temperature protection is desired
There are 4 GND pins. Pins 9 & 10 are for input signal GND
but the flag is not used.
and pins 1 and 23 are for power gnd.
8
ISEN/ /ILIM Current Sense output and program-
POWER SUPPLY BYPASSING
mable current limit. A current propor-
tional to output current is sourced by
Bypass capacitors to power supply terminals Vs and V_DD
must be connected physically close to the pins to prevent
this pin. Typically this pin is connected
to a resistor for programmable current
erratic, low efficiency operation and excessive ringing at the
limit or transconductance operation.
outputs. Electrolytic capacitors, at least 10µF per output amp,
9,10 GND(Sig) Ground connection for all internal digital
are required for suppressing Vs to PGND noise. High qual-
and low current analog circuitry.
ity ceramic capacitors (X7R) 1µF or greater should also be
used. Only capacitors rated for switching applications should
be considered.
The bypass capacitors must be located as close to the power
supply pins as possible (due to the very fast switching times
Y _{of the outputs, the inductance of 1 inch of circuit trace could}
cause noticeable degradation in performance). The bypassing
requirements of V_DD are less stringent, but still necessary. A
R 0.1µF to 0.47µF capacitor connected directly between the V_DD
and GND (SIG) pins will suffice.
PIN DESCRIPTIONS
A _{Pin #}
1,23
Name
PGND
Description
Power ground, high current ground
2,3
Bout
I ^{N 4,5,19,20 VS}
return path of the motor.
Half bridge output B
High voltage supply
6
SCin
Short circuit detect, CMOS. This pin
can be used as a flag for a short cir-
cuit condition. Under normal operation
this pin will be logic low. When a short
circuit is detected, or output current
I ^{M exceeds approximately 10A, this pin}
will change to logic high and the output
will be latched off. Grounding this pin
disables short circuit protection. This
pin should be left open if short circuit
L _{protection is desired but the flag is not}
used. Short circuit protection functions
independently of programmable current
E _{limit (ISEN). It is nessesary to bypass}
the SCin pin with a 14-47pF ceramic
capacitor. This capacitor will add a de-
lay to the short circuit response but the
R_{device will still be able to protect itself}
P^{against short circuit and over current.}
11
12
13,14
15
16
17
18
21,22
FAULT
CPWM
VDD
VREF
DIR
PWM
DISABLE
Aout
Protection circuit flag output, CMOS.
The fault pin will be logic high when the
output MOSFETs have been automati-
cally latched off because of a short circuit
or over temperature condition. This pin
should be left open if not used.
An external timing capacitor is connected
to this pin to set the frequency of the
internal oscillator and ramp generator
for analog control mode. The capaci-
tor value (pF) = 4.05x10⁷/F_SW, where
F_SW = the desired switching frequency.
This pin is grounded for digital control
mode.
5V supply for input logic and low voltage
analog circuitry.
Reference voltage. Can be used at
low current for biasing analog loop
circuits.
Direction logic input, CMOS/TTL. De-
termines the active output MOSFETs
in two quadrant digital control mode.
This pin should be grounded for analog
control mode.
CMOS/TTL input for digital PWM con-
trol, or 1-4V analog input for duty cycle
control in analog control mode.
Disable logic input, CMOS/TTL. Logic
low on this pin allows the SA56 to func-
tion normally. When pulled to logic high,
all four output MOSFETs are disabled.
Pulling this pin high, then low will reset
a latched fault condition caused by a
short circuit or over temperature fault.
Half bridge output A
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