CS1610 Datasheet, PDF (5/17 Pages) Cirrus Logic – TRIAC Dimmable LED Driver IC

CS1610/11/12/13
Parameter
Condition
Symbol
Min
Typ
Max Unit
Second Stage Current Sense
Overcurrent Protection Threshold
Sense Resistor Short Threshold
Peak Control Threshold
Leading-edge Blanking
Delay to Output
V_OCP(th)
-
V_OLP(th)
-
V_{Pk_Max(th)}
-
t_LEB
-
-
1.69
-
V
200
-
mV
1.4
-
V
550
-
ns
-
100
ns
Second Stage Pulse Width Modulator
Minimum On Time
-
0.55
Maximum On Time
-
8.8
Minimum Switching Frequency
Maximum Switching Frequency
t_FB(Min)
t_FB(Max)
-
625
-
200
Second Stage Gate Driver
Output Source Resistance
Output Sink Resistance
Rise Time
Fall Time
(Note 5)
(Note 5)
V_DD = 12V
V_DD = 12V
C_L = 0.25nF
C_L = 0.25nF
Z_OUT
Z_OUT
-
24
-
11
-
-
-
-
Second Stage Protection
Overcurrent Protection (OCP)
Overvoltage Protection (OVP)
Open Loop Protection (OLP)
V_OCP(th)
-
1.69
V_OVP(th)
-
1.25
V_OLP(th)
-
200
External Overtemperature Protection (eOTP), Boost Peak Current, Second Stage Frequency Gain
Pull-up Current Source – Maximum
Conductance Accuracy
(Note 3)
I_CONNECT
-
80
-
-
Conductance Offset
(Note 3)
-
± 250
Current Source Voltage Threshold
V_CONNECT(th)
-
1.25
Internal Overtemperature Protection (iOTP)
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
(Note 4)
(Note 4)
T_SD
T_SD(Hy)
-
135
-
14
-
s
-
s
-
Hz
-
kHz
-

-

30
ns
20
ns
-
V
-
V
-
mV
-
A
±5

-
nS
-
V
-
ºC
-
ºC
Notes:
1.
The CS1610/11/12/13 has an internal shunt regulator
defined in the VDD Supply Voltage section on page 4.
that
limits
the
voltage
on
the
VDD
pin.
V_Z,
the
shunt
regulation
voltage,
is
2. External circuitry should be designed to ensure that the ZCD current drawn from the internal clamp diode when it is forward biased
does not exceed specification.
3. The conductance is specified in Siemens (S or 1/). Each LSB of the internal ADC corresponds to 250nS or one parallel 4M
resistor. Full scale corresponds to 256 parallel 4M resistors or 15.625k.
4. Specifications are guaranteed by design and are characterized and correlated using statistical process methods.
5. For test purposes, load capacitance (C_L) is 0.25nF and is connected as shown in the following diagram.
VDD
VDD
GD
S1
R1
CS
GND
CL
0. 25 nF
+15V
Buffer
R2 _-15V
TP
R3
GD OUT
S2
DS929F5
5