SA07 Datasheet, PDF (4/5 Pages) Cirrus Logic – PULSE WIDTH MODULATION AMPLIFIERS

SA07
OPERATING
CONSIDERATIONS
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Please read Application Note 30 on "PWM Basics". Refer
to Application Note 1 "General Operating Considerations" for
helpful information regarding power supplies, heat sinking
and mounting. Visit www.apexmicrotech.com for design tools
that help automate pwm filter design and heat sink selection.
The "Application Notes" and "Technical Seminar" sections
contain a wealth of information on specific types of applica-
tions. Information on package outlines, heat sinks, mounting
hardware and other accessories are located in the "Packages
and Accessories" section. Evaluation Kits are available for most
Apex product models, consult the "Evaluation Kit" section for
details. For the most current version of all Apex product data
sheets, visit www.apexmicrotech.com.
CLOCK CIRCUIT AND RAMP GENERATOR
The clock frequency is internally set to a frequency of ap-
proximately 1MHZ. The CLK OUT pin will normally be tied to
the CLK IN pin. The clock is divided by two and applied to an
RC network which produces a ramp signal at the RAMP pin.
An external clock signal can be applied to the CLK IN pin for
synchronization purposes. If a clock frequency lower than 1MHz
is chosen an external capacitor must be tied to the RAMP pin.
This capacitor, which parallels an internal capacitor, must be
selected so that the ramp oscillates 2.5 volts p-p with the lower
peak 1.25 volts above ground.
BYPASSING
Adequate bypassing of the power supplies is required for
proper operation. Failure to do so can cause erratic and low
efficiency operation as well as excessive ringing at the out-
puts. The Vs supply should be bypassed with at least a 1µF
ceramic capacitor in parallel with another low ESR capacitor
of at least 10µF per amp of output current. Capacitor types
rated for switching applications are the only types that should
be considered. The bypass capacitors must be physically
connected directly to the power supply pins. Even one inch of
lead length will cause excessive ringing at the outputs. This is
due to the very fast switching times and the inductance of the
lead connection. The bypassing requirements of the Vcc supply
are less stringent, but still necessary. A .1µF to .47µF ceramic
capacitor connected directly to the Vcc pin will suffice.
NOISE FILTERING
Switching noise can enter the SA07 through the INT OUT
to +PWM connection. A wise precaution is to low pass filter
this connection. Adjust the pass band of the filter to 10 times
the bandwidth required by the application. Keep the resistor
value to 100 ohms or less since this resistor becomes part of
the hysteresis circuit on the pwm comparator.
PCB LAYOUT
The designer needs to appreciate that the SA07 combines
in one circuit both high speed high power switching and low
level analog signals. Certain layout rules of thumb must be
considered when a circuit board layout is designed using the
SA07:
1. Bypassing of the power supplies is critical. Capacitors
must be connected directly to the power supply pins with
very short lead lengths (well under 1 inch). Ceramic chip
capacitors are best.
2. Make all ground connections with a star pattern at pin 7.
3. Beware of capacitive coupling between output connections
and signal inputs through the parasitic capacitance between
layers in multilayer PCB designs.
4. Do not run small signal traces between the pins of the output
section (pins 11-16).
5. Do not allow high currents to flow into the ground plane.
6. Separate switching and analog grounds and connect the
two only at pin 7 as part of the star pattern.
INTEGRATOR
The integrator provides the inverted signal for negative
feedback and also the open loop gain for the overall applica-
tion circuit accuracy. Recommended value of C_INT is 10 pF
for stability. However, poles and zeroes can be added to the
circuit for overall loop stability as required.
CURRENT LIMIT
There are two load current sensing pins, I SENSE A and I
SENSE B. The two pins can be shorted in the voltage mode
connection but both must be used in the current mode con-
nection (see figures A and B). It is recommended that R_LIMIT
resistors be non-inductive. Load current flows in the I SENSE
pins. To avoid errors due to lead lengths connect the I LIMIT/
SHDN pin directly to the R_LIMIT resistors (through the filter
network and shutdown divider resistor) and connect the R_LIMIT
resistors directly to the GND pin. Do not connect R_LIMIT sense
resistors to the ground plane.
APEX MICROTECHNOLOGY CORPORATION • 5980 NORTH SHANNON ROAD • TUCSON, ARIZONA 85741 • USA • APPLICATIONS HOTLINE: [phone]
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