AOZ1052PI Datasheet, PDF (9/14 Pages) Alpha & Omega Semiconductors – EZBuck™ 4A Synchronous Buck Regulator

AOZ1052PI
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
V_O
=
I_L



E
S
R_CO
+
-₈----_-----_f--¹-_-----_C-----_O--_
where,
C_O is output capacitor value, and
ESR_CO is the equivalent series resistance of the output
capacitor.
When a low ESR ceramic capacitor is used as the output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
V_O
=
I_L

------------¹-------------
8  f  C_O
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
V_O = I_L  ESR_CO
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum capacitors are
recommended as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It can
be calculated by:
I_{CO_RMS}
=
--^----^I--^L--
12
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, the output capacitor could
be overstressed.
Loop Compensation
The AOZ1052PI employs peak current mode control for
ease of use and fast transient response. Peak current
mode control eliminates the double pole effect of the
output L&C filter. It also greatly simplifies the
compensation loop design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
f_P1
=
----------------¹------------------
2  _CO  _RL
The zero is a ESR zero due to the output capacitor and
its ESR. It is can be calculated by:
f_Z1
=
-----------------------¹-------------------------
2  C_O  ESR_CO
where;
C_O is the output filter capacitor,
R_L is load resistor value, and
ESR_CO is the equivalent series resistance of output capacitor.
The compensation design shapes the converter control
loop transfer function for the desired gain and phase.
Several different types of compensation networks can be
used with the AOZ1052PI. For most cases, a series
capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1052PI, FB and COMP are the inverting input
and the output of the internal error amplifier. A series
R and C compensation network connected to COMP
provides one pole and one zero. The pole is:
f_P2
=
----------------^G-----^E----^A-----------------
2  C_C  G_VEA
where;
G_EA is the error amplifier transconductance, which is 200 x 10^-6
A/V,
G_VEA is the error amplifier voltage gain, which is 500V/V, and
C_C is the compensation capacitor in Figure 1.
Rev. 0.5 September 2012
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