AOZ5007 Datasheet, PDF (11/16 Pages) Alpha & Omega Semiconductors – High-Current, High-Performance DrMOS Power Module

AOZ5007
This delay is typically 170 ns and intended to prevent
spurious triggering of the tri state mode which may be
caused either by noise induced glitches in the PWM
waveform or slow rise and fall times.
Table 1. PWM Input and Tri State Thresholds
Thresholds 
AOZ5007QI
AOZ5007QI-01
V_PWMH
3.9V
2V
V_PWML
1.0 V
1V
V_TRIH
1.3V
1.3V
V_TRIL
3.7V
1.75 V
Note: See Figure 16 for propagation delays and tri state window.
Diode Mode Emulation of Low Side MOSFET (SMOD)
AOZ5007QI can be operated in the diode emulation or
skip mode using the SMOD pin. This is useful if the
converter has to operate in asynchronous mode during
start up, light load or under pre bias conditions. If SMOD
is taken high, the controller will use the PWM signal as
reference and generate both the high and low side
complementary gate drive outputs with the minimal
delays necessary to avoid cross conduction. When the
pin is taken low the HS FET drive is not affected but
diode emulation mode is activated for the LS FET. See
Table 2 for a comprehensive view of all logic inputs and
corresponding drive conditions.
Table 2. Control Logic Truth Table
DISB SMOD PWM
GH
L
X
X
L
H
L
H
H
H
L
L
L
H
H
Tri State
L
H
H
H
H
H
H
L
L
GL
L
L
See Note
L
L
H
Note: Diode emulation mode is activated when SMOD pin is held low.
Gate Drives
AOZ5007QI has an internal high current high speed
driver that generates the floating gate drive for the
HS FET and a complementary drive for the LS FET.
Propagation delays between transitions of the PWM
waveform and corresponding gate drives are kept to the
minimum. An internal shoot through protection scheme
ensures that neither MOSFET turns on while the other
one is still conducting, thereby preventing shoot through
condition of the input current. When the PWM signal
makes a transition from H  L or L  H, the
corresponding gate drive GH or GL begins to turn off.
The adaptive timing circuit monitors the falling edge of
the gate voltage and when the level goes below 1V, the
complementary gate driver is turned on. The dead time
between the two switches is minimized, at the same time
preventing cross conduction across the input bus. The
adaptive circuit also monitors the switching node VSWH
and ensures that transition from one MOSFET to another
always takes place without cross conduction, even under
transient and abnormal conditions of operation.
The gate pins GH and GL are brought out on pins 6 and
36 respectively. However these connections are not
made directly to MOSFET gate pads and their voltage
measurement may not reflect the actual gate voltage
applied inside the package. The gate connections are
primarily for functional tests during manufacturing and no
connections should be made to them in the application.
Thermal Shutdown
The module temperature is internally sensed and an
alarm is asserted if it exceeds 150 °C. The alarm is reset
when the temperature cools down to 135 °C. The THDN
is an open drain pin that is pulled to CGND to indicate an
over temperature condition. It may be pulled up to VCIN
through a resistor for monitoring purposes.
PCB Layout Guidelines
AOZ5007 is a high current module rated for operation up
to 1.5 MHz. This requires extremely fast switching
speeds to keep the switching losses and device
temperatures within limits. Having a robust gate driver
integrated in the package helps to minimise the
driver-to-MOSFET gate pad connections without
involving the parasitics of the package or PCB traces.
While excellent switching speeds are achieved,
correspondingly high levels of dv/dt and di/dt will be
observed throughout the power train which requires
careful attention to PCB layout to minimise voltage
spikes and other transients. As with any synchronous
buck converter layout the critical requirement is to
minimise the area of the primary switching current loop,
formed by the HS FET, LS FET and the input bypass
capacitor C_in. The PCB design is somewhat simplified
because of the optimized pin out in AOZ5007QI. The
bulk of VIN and PGND pins are located adjacent to each
other and the input bypass capacitors should be placed
as close as possible to these pins. The area of the
secondary switching loop, formed by LS FET, output
inductor and output capacitor C_out is the next critical
parameter. The ground plane should be extended and
the negative pins of C_out should be returned to it, again
as close as possible to the device pins.
The AOZ5007QI is extremely efficient. MOSFETs in the
package are directly attached to individual exposed pads
to simplify thermal management. Both VIN and VSWH
pads should be attached to large areas of PCB copper.
Thermal reliefs should be avoided to ensure proper heat
Rev. 1.1 October 2011
www.aosmd.com
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