APA3169 Datasheet, PDF (38/53 Pages) Anpec Electronics Coropration – 20W Stereo Digital Class-D Audio Power Amplifier with EQ, DRC and 2.1 Mode

APA3169
Function Description (Cont.)
Table 1. Serial Control Interface Register Summary (Cont.)
Sub Address
Register Name
No. of Bytes
Contents
u[31:26], b0[25:0]
u[31:26], b1[25:0]
0x5F
pseudo_ch2_bq[1]
20
u[31:26], b2[25:0]
u[31:26], a1[25:0]
u[31:26], a2[25:0]
0x60
Ch4 output mixer
ch4_output_mixer1
8
ch4_output_mixer0
0x61
Ch4 input mixer
ch4_input_mixer1
8
ch4_input_mixer0
0x62-0xF0
Reserved(1)
Note (1): Reserved register should not be accessed
All DAP coefficients are 3.23 format unless specified otherwise.
Initialization Values
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0040 0000
0x0040 0000
Clock Control Register (0x00)
The clocks and data rates are automatically determined by the APA3169. The clock control register contains the auto-
detected clock status. Bits D7-D5 reflect the sample rate. Bits D4-D2 reflect the MCLK frequency.
Table 2. Clock Control Register (0x00)
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
-
-
-
-
-
0
0
1
-
-
-
-
-
0
1
0
-
-
-
-
-
0
1
1
-
-
-
-
-
1
0
0
-
-
-
-
-
1
0
1
-
-
-
-
-
1
1
0
-
-
-
-
-
1
1
1
-
-
-
-
-
-
-
-
0
0
0
-
-
-
-
-
0
0
1
-
-
-
-
-
0
1
0
-
-
-
-
-
0
1
1
-
-
-
-
-
1
0
0
-
-
-
-
-
1
0
1
-
-
-
-
-
1
1
0
-
-
-
-
-
1
1
1
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
0
Note (1): Reserved registers should not be accessed.
Note (2): Default values are in bold
Note (3): Only available for 44.1kHz and 48kHz rates.
Note (4): Rate only available for 32/44.1/48kHz sample rates.
FUNCTION
fS=32kHz sample rate
fS=88.2/96kHz sample rate
fS=176.4/192kHz sample rate
fS=44.1/48kHz sample rate ⁽²⁾
Reserved⁽¹⁾
Reserved⁽¹⁾
Reserved⁽¹⁾
Reserved⁽¹⁾
MCLK frequency=64xfS ⁽³⁾
MCLK frequency=128xfS ⁽³⁾
MCLK frequency=192xfS ⁽⁴⁾
MCLK frequency=256xfS ⁽²⁾
MCLK frequency=384xfS
MCLK frequency=512xfS
Reserved ⁽¹⁾
Reserved ⁽¹⁾
Reserved ⁽¹⁾
Reserved ⁽¹⁾
Copyright © ANPEC Electronics Corp.
38
Rev. A.4 - Jan., 2013
www.anpec.com.tw