English
Language : 

APL3540 Datasheet, PDF (3/19 Pages) Anpec Electronics Coropration – High-Side Power Distribution Controller
APL3540
Recommended Operating Conditions (Note 3)
Symbol
Parameter
VIN
VIN Input Voltage (VIN to GND)
VEN
EN to GND Voltage
TA
Ambient Temperature
TJ
Junction Temperature
Note 3: Refer to the typical application circuit
Range
Unit
10 to 26
V
0 to 5
V
-40 to 85
oC
-40 to 125
oC
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=19V, VEN =5V and TA= -40 to 85 oC. Typical values are at TA=25oC.
Symbol
Parameter
Test Conditions
APL3540
Unit
Min. Typ. Max.
UNDER-VOLTAGE LOCKOUT (UVLO) AND SUPPLY CURRENT
VUVLO VIN UVLO Threshold Voltage
VIN rising, TA= -40 to 85 oC
VIN UVLO Hysteresis
7.0
7.5
8.0
V
0.3
0.4
0.5
V
TD(ON)
Power-On Delay Time
IVIN
VIN Supply Current
WRONG VIN INPUT VOLTAGE PROTECTION
VIN >VUVLO, VEN=5V, and
VVINSEL(H)>VVINSEL> VVINSEL(L)
No load, VEN =5V
No load, VEN =0V
5
8.5
12
ms
-
750 1200 µA
-
400 600 µA
VVINSEL(L)
VVINSEL(H)
VINSEL Low Detection Rising
Threshold
VINSEL Low Detection Falling
Threshold
VINSEL High Detection Rising
Threshold
VINSEL High Detection Falling
Threshold
VIN rising, IC is on, VIN=10V to 21V
VIN falling, IC is off, VIN=10V to 21V
VIN rising, IC is off, VIN=10V to 21V
VIN falling, IC is on, VIN=10V to 21V
1.223 1.275 1.305 V
1.148 1.200 1.230 V
1.748 1.800 1.830 V
1.673 1.725 1.755 V
VINSEL Input Current
VINSEL Low Detection Debounce
VINSEL High Detection Debounce
GATE DRIVER
VVINSEL=40V
VVINSEL falling, VVINSEL < VVINSEL(L)
VVINSEL rising, VVINSEL > VVINSEL(H)
-
-
1
µA
-
10
-
µs
-
10
-
µs
VDRV-OUT
DRV to VOUT Voltage
DRV Source Current
VDRV-VOUT, VIN=19
VDRV=10V, VDRV-VOUT=2.5
4.3
4.6
4.9
V
155 185 215 µA
DRV Discharge Resistance
PROTECTIONS
Any fault condition and shutdown
(connected from DRV to VOUT), VDRV=5V, 1.8
2.0
2.2
kΩ
VOUT=GND
IOCSET
Under-Voltage Protection Threshold VOUT falling, VOUT/VIN
Under-Voltage Protection Debounce
OCSET Source Current
No load, VVINSEL=1.5V, VEN=5V,
VOCSET=18.9V
OCSET Offset Voltage
65
70
-
5
45
50
-10
0
75
%
-
µs
55
µA
10
mV
Over-Current Debounce
-
10
-
µs
Copyright © ANPEC Electronics Corp.
3
Rev. A.9 - Oct., 2013
www.anpec.com.tw