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APW8811 Datasheet, PDF (18/23 Pages) Anpec Electronics Coropration – System Power PWM Controller for Notebook Computers
APW8811
Application Information (Cont.)
Layout Consideration (Cont.)
• Keep the switching nodes (UGATEx, LGATEx, BOOTx,
and PHASEx) away from sensitive small signal nodes
(REF, ILIMx, and FBx) since these nodes are fast mov-
ing signals. Therefore, keep traces to these nodes as
short as possible and there should be no other weak
signal traces in parallel with theses traces on any layer.
• The signals going through theses traces have both
high dv/dt and high di/dt, with high peak charging and
discharging current. The traces from the gate drivers
to the MOSFETs (UGATEx and LGATEx) should be short
and wide.
• Place the source of the high-side MOSFET and the
drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane be-
tween the two pads reduces the voltage bounce of
the node.
• Decoupling capacitor, the resistor dividers, boot
capacitors, and current-limit stetting resistor should
be close to their pins. (For example, place the
decoupling ceramic capacitor near the drain of the
high-side MOSFET as close as possible. The bulk
capacitors are also placednear the drain.)
• The input capacitor should be near the drain of the
upper MOSFET; the high quality ceramic decoupling
capacitor can be put close to the VCC and GND pins;
the output capacitor should be near the loads. The
input capacitor GND should be close to the output ca-
pacitor GND and the lower MOSFET GND.
• The drain of the MOSFETs (VIN and PHASEx nodes)
should be a large plane for heat sinking. And PHASEx
pin traces are also the return path for UGATEx. Con-
nect these pins to the respective converter’s upper
MOSFET source.
• The controller used ripple mode control. Build the re-
sistor divider close to the FB1 pin so that the high
impedance trace is shorter when the output voltage is
in adjustable mode. And the FB1 pin traces can’t be
close to the switching signal traces (UGATEx, LGATEx,
BOOTx, and PHASEx).
• The PGND trace should be a separate trace, and in-
dependently go to the source of the low-side MOSFETs
for current-limit accuracy.
Copyright © ANPEC Electronics Corp.
18
Rev. A.3 - Sep., 2012
TQFN4x4-24A
www.anpec.com.tw