APW7088 Datasheet, PDF (16/25 Pages) Anpec Electronics Coropration – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers

APW7088
Application Information
Output Voltage Setting
The output voltage is adjustable from 0.85V to 2.5V with a
resistor-divider connected with FB, AGND, and converter’s
output. Using 1% or better resistors for the resistor-di-
vider is recommended. The output voltage is determined
by :
VOUT = VDAC × 1+ ^RTOP 
 ^RGND 
Where V_DAC is the internal digital VID programmable ref-
erence voltage, the R is the resistor connected from
TOP
converter’s output to FB and R is the resistor con-
GND
nected from FB to AGND. Suggested R_GND is in the range
from 1K to 20KΩ. To prevent stray pickup, locate resis-
tors R_TOP and R_GND close to the APW7088.
PWM Compensation
The output LC filter of a step down converter introduces a
double pole, which contributes with -40dB/decade gain
slope and 180 degrees phase shift in the control loop. A
compensation network among COMP, FB, and V
OUT
should be added. The compensation network is shown
in Figure 8. The output LC filters consists of the
output inductors and output capacitors. For two-phase
convertor, when assuming V_IN1=V_IN2=V_IN, L1=L2=L, the
transfer function of the LC filter is given by :
GAIN_LC
=
s² ×
1+ s × ESR × C_OUT
1
2
L
×
COUT
+
s
×
ESR
×
C_OUT
+1
The poles and zero of this transfer functions are :
F_LC =
2×π×
1
1
2
L
×
C_OUT
F_ESR
=
1
2 × π × ESR × C_OUT
The F_LC is the double-pole frequency of the two-phase LC
filters, and F_ESR is the frequency of the zero introduced by
the ESR of the output capacitors.
V_PHASE1
L1=L
V_OUT
V_PHASE2
L2=L
C_OUT
ESR
Figure 5. The Output LC Filter
F_LC
-40dB/dec
F_ESR
-20dB/dec
Frequency(Hz)
Figure 6. Frequency Resopnse of the LC filters
The PWM modulator is shown in figure 7. The input is the
output of the error amplifier and the output is the PHASE
node. The transfer function of the PWM modulator is given
by :
GAIN_PWM
=
V_IN
∆V_OSC
V_IN
Driver
OSC
PWM
Comparator
∆V_OSC
PHASE
Output of Error
Amplifier
Driver
Figure 7. The PWM Modulator
The compensation network is shown in figure 8. It pro-
vides a close loop transfer function with the highest zero
crossover frequency and sufficient phase margin.
The transfer function of error amplifier is given by:
GAIN_AMP
=
V_COMP
V_OUT
=
1
sC1
//

R2
+
R1//R3 +
1
sC2


1 _
 ^sC3 
=
R1+ R3
×


s
+
R2
1
×
C2


×

s
+
(R1+
1
R3)×
C3

R1× R3 × C1
s

s
+
C1+ C2
R2 × C1× C2


×


s
+
R3
1
×
C3


Copyright © ANPEC Electronics Corp.
16
Rev. A.4 - Feb., 2009
www.anpec.com.tw