APA0713 Datasheet, PDF (10/19 Pages) Anpec Electronics Coropration – 1.1W Mono Low-Voltage Audio Power Amplifier

APA0713
Application Information
BTL Operation
OP1
Vbias
VO+
OP2
RL
VO-
Figure 1: APA0713 power amplifier internal configuration
The power amplifier OP1 gain is set by external gain
setting, while the second amplifier OP2 is internally
fixed in a unity-gain, inverting configuration. Figure 1
shows that the output of OP1 is connected to the input to
OP2, which results in the output signals of with both
amplifiers with identical in magnitude, but out of phase
180°. Consequently, the differential gain for each chan-
nel is 2X (Gain of SE mode).
By driving the load differentially through outputs VO+ and
VO-, an amplifier configuration commonly referred to as
bridged mode is established. The BTL mode operation is
different from the classical single-ended SE amplifier con-
figuration where one side of its load is connected to
ground.
The BTL amplifier design has a few distinct advantages
over the SE configuration, as it provides differential drive
to the load, thus doubling the output swing for a specified
supply voltage.
Four times the output power is possible as compared
with a SE amplifier under the same conditions. A BTL
configuration, such as the one used in the APA0713, also
creates a second advantage over SE amplifiers. Since
the differential outputs, VO+ and VO-, are biased at half-
supply, no need DC voltage exists across the load. This
eliminates the need for an output coupling capacitor
which is required in a single supply, SE configuration.
Input Capacitor, C_I
In the typical application, an input capacitor, C_I, is re-
quired to allow the amplifier to bias the input signal to the
proper DC level for optimum operation. In this case, C
I
and the minimum input impedance R_I from a high-pass
filter with the corner frequency are determined in the fol-
lowing equation :
FC(highpass ) = ¹
(1)
2πRICI
The value of C_I is important to consider as it directly af-
fects the low frequency performance of the circuit. Con-
sider the example where R_I is 100KΩ and the specifi-
cation calls for a flat bass response down to 40Hz. Equa-
tion is reconfigured as followed :
CI = ¹
2πRIFC
(2)
Consider input resistance variation, the C_I is 0.04µF so
one would likely choose a value in the range of 0.1µF
to 1.0µF.
A further consideration for this capacitor is the leakage path
from the input source through the input network (R_I+R_F,
C ) to the load.
I
This leakage current creates a DC offset voltage at the
input to the amplifier that reduces useful headroom, es-
pecially in high gain applications. For this reason, a low-
leakage tantalum or ceramic capacitor is the best choice.
When polarized capacitors are used, the positive side
of the capacitor should face the amplifier input in most
applications as the DC level there is held at V_DD/2, which
is likely higher than the source DC level. Please note that
it is important to confirm the capacitor polarity in the
application.
Effective Bypass Capacitor, C_bypass
As other power amplifiers, proper supply bypassing is
critical for low noise performance and high power supply
rejection.
The capacitors located on the bypass and power supply
pins should be as close to the device as possible. The
effect of a larger half supply bypass capacitor will improve
Copyright © ANPEC Electronics Corp.
10
Rev. A.2 - Apr., 2012
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