APW8819 Datasheet, PDF (1/28 Pages) Anpec Electronics Coropration – DDR TOTAL POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER WITH 1.5A LDO

APW8819
DDR TOTAL POWER SOLUTION
SYNCHRONOUS BUCK CONTROLLER WITH 1.5A LDO
Features
General Description
Buck Controller (VDDQ)
• High Input Voltages Range from 3V to 28V Input
Power
• Provide 1.8V (DDR2), 1.5V (DDR3) or Adjustable
Output Voltage from 0.5V to 2V
- ±1% Accuracy Over-Temperature
• Build in VREF Voltage 1.8V ±1% Accuracy over
Temperature
• Integrated MOSFET Drivers
• Integrated Bootstrap Forward P-CH MOSFET
• Excellent Line and Load Transient Responses
• PFM Mode for Increased Light Load Efficiency
• Selectable 300kHz/400kHz/500kHz Switching
Frequebcies
• Integrated MOSFET Drivers and Bootstrap Diode
• S3 and S5 Pins Control The Device in S0, S3, or
S4/S5 State
• Power Good Monitoring
• 50% Under-Voltage Protection (UVP)
• 125% Over-Voltage Protection (OVP)
• Adjustable Current-Limit Protection
- Using Sense Low-Side MOSFET R_DS(ON)
• QFN-20 3mmx3mm Package (QFN-20) and
QFN-16 3mmx3mm Thin Package (TQFN-16)
• Lead Free Available (RoHS Compliant)
+1.5A LDO Section (VTT)
• Souring or Sinking Current up to 1.5A
• Fast Transient Response for Output Voltage
• Output Ceramic Capacitors Support at Least
10µF MLCC
• VTT and VTTREF Track at Half the VDDQSNS by
Internal Divider
• ±20mV Accuracy for VTT and VTTREF
• Independent Over-Current-Limit (OCL)
• Thermal Shutdown Protection
The APW8819 integrates a synchronous buck PWM con-
troller to generate VDDQ, a sourcing and sinking LDO
linear regulator to generate VTT. It provides a complete
power supply for DDR2 and DDR3 memory system. It
offers the lowest total solution cost in system where space
is at a premium.
The APW8819 provides excellent transient response and
accurate DC voltage output in PFM Mode. In Pulse Fre-
quency Mode (PFM), the APW8819 provides very high ef-
ficiency over light to heavy loads with loading-modulated
switching frequencies.
The APW8819 is equipped with accurate current-limit,
output under-voltage, and output over-voltage protections.
A Power-On- Reset function monitors the voltage on VCC
prevents wrong operation during power on.
The LDO is designed to provide a regulated voltage with
bi-directional output current for DDR-SDRAM termination.
The device integrates two power transistors to source or
sink current up to 1.5A. It also incorporates current-limit
and thermal shutdown protection.
An internal resistor divider is used to provide a half volt-
age of VDDQSNS for VTTREF and VTT Voltage. The VTT
output voltage is only requiring 20µF of ceramic output
capacitance for stability and fast transient response. The
S3 and S5 pins provide the sleep state for VTT (S3 state)
and suspend state (S4/S5 state) for device, when S5 and
S3 are both pulled low the device provides the soft-off for
VTT and VTTREF.The APW8819 is available in
3mmx3mm 20-pin QFN and 3mmx3mm 16-pin TQFN
packages.
Applications
• DDR2, and DDR3 Memory Power Supplies
• SSTL-2 SSTL-18 and HSTL Termination
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
1
Rev. A.6 - May, 2013
www.anpec.com.tw