X3DC19P1S Datasheet, PDF (5/7 Pages) Anaren Microwave – Doherty Combiner

Model X3DC19P1S
Rev A
Definition of the Specifications
To guarantee the part performance in Doherty architecture, the part is specified in Doherty operation for maximum
power condition and low power condition. The following specification definition assumes the extra port extension is
deembeded from the raw S parameter and the parts is measured with Pin n connected to Port n (where n=1, 2, 3, 4).
• Maximum power condition
Under the maximum power condition, the symmetrical Doherty architecture requires main amplifier and peak amplifier to
work at full capacity with the optimum termination (50 Ω). The two amplifiers should deliver RF power of equal
magnitude and 90 degree phase difference. Doherty combiner functions as a coherent power combiner and supplies the
90 degree phase compensation. The following specification is defined with 50 Ω port impedance at three ports for this
condition.
Parameter
Return Loss
Insertion Loss
Phase Imbalance
Amplitude Imbalance
Definition
The impedance match at
the combining port to a
50Ω system.
The combined power
divided by the sum of
input power under the
perfect combining
condition.
The phase difference
between Peak-Combined
path and Main-Combined
path at ω_c = 1930MHz
The magnitude difference
between Peak-Combined
path and Main-Combined
path.
Mathematical Representation
20log S₁₁
( ) 10log S₁₂₃ + S₁₂₄
Phase (S₁₄ (ω_c ))– Phase (S₁₃(ω_c ))
( ) 20log S₁₄ − 20log S₁₃
2
• Low power condition
Under low power condition, the Doherty operation turns off peak amplifier and requires main amplifier to be terminated
with double of the optimum impedance (100 Ω). With the peak port open, Doherty combiner servers as an impedance
transformer transforming 50 Ω at combining port to 100 Ω at main amplifier port. The following specification is defined
under the port impedance condition of Port 1 (Combining Port) 50 Ω, Port 4 (Main Amp Port) 100 Ω and Port 3 (Peak Amp
Port) open.
Parameter
Return Loss
Insertion Loss
Definition
The impedance match of
the 50 to100 Ω
transformer.
The output power divided
by input power.
Mathematical Representation
20log S₁₁
20log S ₄₁
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