AAT3232 Datasheet, PDF (6/10 Pages) Advanced Analogic Technologies – 300mA CMOS Low Drop Out Linear Regulator

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AAT3232
300mA CMOS Low Drop Out Linear Regulator
Detailed Description
The AAT3232 is intended for use in systems
where minimal current consumption is desired.
During steady state operation, ground current is
30 µA typical. All remaining current is available to
run the load. This part can also be run with drop
out voltages as small as 300 mV allowing very
efficient systems to be designed. Several
compromises have been made for this device to
operate with both low steady state current
consumption and very low drop out voltage. The
primary compromise is the requirement of larger
capacitors over those required by other power
hungry high performance LDO’s. Since the
AAT3232 has considerably faster response than
some ultra low current consumption LDOs
available, it should not be considered a low
performance LDO. The second compromise is
the inability to sink current. If current is sourced
by the load rather than sunk by the load, the
AAT3232 will simply stop supplying current rather
than actively reducing the output voltage. As long
as the output voltage does not exceed the
absolute maximum specification, the AAT3232 will
not be damaged.
Output Capacitor
Output capacitor size is dependent upon the
magnitude and the rate of change of the load
variation. 10 µF tantalum or 5.6 µF ceramic is
needed only if the load will change by 270 mA
(90% of Imax) in less than a couple of
microseconds. Smaller capacitors can be used if
the output current step size, or rate of change, is
less. (See graph titled Output Capacitance vs.
Load Current Step Size.) In addition, if adequate
bypassing is used at the load, the output capacitor
near the LDO can be reduced.
The AAT3232 has been optimized for operation
with capacitors that are not of the low series
resistance type. There are two benefits of using
an LDO designed to work with series resistance.
First, capacitors sized 10 µF or greater with low
ESR are generally more expensive than the
higher ESR types such as tantalum and
electrolytic. Secondly, output capacitors need not
be placed next to the regulator. Most applications
use a large higher-ESR capacitor placed near the
Output Capacitance vs.
Load Current Step Size
10
9
8
ESR = 1.0Ω
7
ESR = 0.01Ω
6
5
4
3
ESR = 0.5Ω
2
1
0
0
50
100
150
200
250
300
Step size (mA)
regulator and low ESR decoupling capacitors
placed near the load. In cases where very
compact design is desirable, a small 1206 case
size ceramic capacitor and the load are placed
and connected immediately adjacent to the LDO
and the trace from the output pin to the output
capacitor should have at least 5 milliohms of
resistance. For example at least ten squares
should be used on a one ounce copper layer.
Also see Layout Tips, below.
Enable
The enable pin is the on/off switch for the LDO.
When it is a logic high, the LDO is functioning
normally. When it is a logic low, the LDO is in a
low power, shut down mode. It has standard
CMOS voltage levels set by the AAT3232 input
voltage. Voltages at this terminal should be within
the absolute maximum rating (-0.5V, to Vin +
0.5V). The enable pin is internally pulled up so
that it may be left floating for normal operation.
However, since the pull up current is only 500 nA,
if open drain logic is used to drive the enable pin,
several hundred microseconds may be required
for the enable voltage to reach a logic high level.
Cnoise
The LDO's internal reference can be bypassed by
connecting a capacitor from BYP to GND,
reducing most of the internally generated noise
seen at the output. (See graph titled Output
Noise in the previous section.) A large capacitor
on Cnoise also improves the PSRR of the
AAT3232. (See graph titled Power Supply
Rejection Ratio) In addition, a large capacitor
Advanced Analogic Technologies, Inc.
1250 Oakmead Pkwy, Suite 310, Sunnyvale, CA 94086
[phone] Fax [phone]
1-48
3232.2000.05.0.98