AAT3603 Datasheet, PDF (32/35 Pages) Advanced Analogic Technologies – Total Power Solution for Portable Applications

PRODUCT DATASHEET
AAT3603178
Total Power Solution for Portable Applications
LDO1₁
0
0
1
1
LDO2₁
0
0
1
1
LDO3₁
0
0
1
1
LDO4₁
0
0
1
1
LDO5₁
0
0
1
1
LDO1₀
0
1
0
1
LDO2₀
0
1
0
1
LDO3₀
0
1
0
1
LDO4₀
0
1
0
1
LDO5₀
0
1
0
1
LDO1 Output Voltage
3.00V (default)
2.90V
2.85V
2.80V
LDO2 Output Voltage
3.00V (default)
2.90V
2.85V
2.80V
LDO3 Output Voltage
3.00V (default)
2.90V
2.85V
2.80V
LDO4 Output Voltage
3.00V (default)
2.90V
2.85V
2.80V
LDO5 Output Voltage
3.00V (default)
2.90V
2.85V
2.80V
Table 7: LDO Bit Setting for
LDO Output Voltage Level.
Layout Guidance
Figure 10 is the schematic for the evaluation board. The
evaluation board has extra components for easy evalua-
tion; the actual BOM need for a system is shown in Table
9. When laying out the PC board, the following layout
guideline should be followed to ensure proper operation
of the AAT3603:
1. The exposed pad EP must be reliably soldered to
PGND/AGND and multilayer GND. The exposed ther-
mal pad should be connected to board ground plane
and pins 2 and 16. The ground plane should include
a large exposed copper pad under the package with
VIAs to all board layers for thermal dissipation.
2. The power traces, including GND traces, the LX
traces and the VIN trace should be kept short, direct
and wide to allow large current flow. The L1 connec-
tion to the LX pins should be as short as possible.
Use several via pads when routing between layers.
3. The input capacitors (C1 and C2) should be con-
nected as close as possible to CHGIN (Pin 28) and
PGND (Pin 2) to get good power filtering.
4. Keep the switching node LX away from the sensitive
OUTBUCK feedback node.
5. The feedback trace for the OUTBUCK pin should be
separate from any power trace and connected as
closely as possible to the load point. Sensing along a
high current load trace will degrade DC load regula-
tion.
6. The output capacitor C4 and L1 should be connected
as close as possible and there should not be any
signal lines under the inductor.
7. The resistance of the trace from the load return to
the PGND (Pin 2) should be kept to a minimum. This
will help to minimize any error in DC regulation due
to differences in the potential of the internal signal
ground and the power ground.
Quantity
5
2
4
3
1
1
9
8
1
Value
10μF
22μF
4.7μF
0.1μF
0.01μF
3.3μH
100K
10K
1.24K
Designator
C1, C2, C3, C14, C15
C9
C4, C5, C6, C7, C8
C10, C11, C12
C13
L1
R5, R8, R20, R21, R22, R23, R25, R26, R27
R17, R19, R24, R29, R31, R32, R33, R37
R18
Footprint
0603
0805
0603
0402
0402
CDRH2D
0402
0402
0402
Description
Capacitor, Ceramic, X5R, 6.3V, ±20%
Capacitor, Ceramic, 20%, 6.3V, X5R
Capacitor, Ceramic, 20%, 6.3V, X5R
Capacitor, Ceramic, 16V, 10%, X5R
Capacitor, Ceramic, 16V, 10%, X7R
Inductor, Sumida CDRH2D11NP-3R3NC
Resistor, 5%
Resistor, 5%
Resistor, 1%
Table 8: Minimum AAT3603 Bill of Materials.
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3603.2008.06.1.0