AAT2554 Datasheet, PDF (26/33 Pages) Advanced Analogic Technologies – Total Power Solution for Portable Applications

AAT2554
Total Power Solution for Portable Applications
VINB
C1
4.7µF
ADP
C3
4.7µF
VINA _C7
2.2µF
ADP
R7
100K
JP1
3
2
1
EN_BAT
VINB
D1
VINB
R5
100K
R6
100K
JP3
3
2
1
JP2
3
2
1
ENB ^ENA
ENB
EN_BAT
ADP
R4
1K
ENA
U1
16 _VINB
BAT ⁸
11 _ADP
OUTA ⁵
9 _STAT
LX ¹⁵
4 _VINA
FB ¹
13 _ENA
GND ¹⁴
3 _ENB
GND ¹²
6 _{EN_BAT GND} 10
7 _ISET
GND ²
AAT2554
R1
8.06K
VOUTA
L1
VOUTB
R2
118K
FB
C8
100pF
R3
59K
C8 optional for
enhanced step-
down converter
transient
response
VOUTB
C4
4.7µF
VOUTA
C6
2.2µF
Figure 5: AAT2554 Evaluation Board Schematic.
VBAT
1
2
C5
2.2µF
GND
Printed Circuit Board Layout
Considerations
For the best results, it is recommended to physi-
cally place the battery pack as close as possible to
the AAT2554 BAT pin. To minimize voltage drops
on the PCB, keep the high current carrying traces
adequately wide. Refer to the AAT2554 evaluation
board for a good layout example (see Figures 6
and 7). The following guidelines should be used to
help ensure a proper layout.
1. The input capacitors (C1, C3, C7) should con-
nect as closely as possible to ADP (Pin 11),
VINA (Pin 4), and VINB (Pin 16).
2. C4 and L1 should be connected as closely as
possible. The connection of L1 to the LX pin
should be as short as possible. Do not make the
node small by using narrow trace. The trace
should be kept wide, direct, and short.
3. The feedback pin (Pin 1) should be separate
from any power trace and connect as closely as
possible to the load point. Sensing along a high-
current load trace will degrade DC load regula-
tion. Feedback resistors should be placed as
closely as possible to the FB pin (Pin 1) to mini-
mize the length of the high impedance feedback
trace. If possible, they should also be placed
away from the LX (switching node) and inductor
to improve noise immunity.
4. The resistance of the trace from the load return
GND (Pins 2, 10, 12, and 14) should be kept to
a minimum. This will help to minimize any error
in DC regulation due to differences in the poten-
tial of the internal signal ground and the power
ground.
5. A high density, small footprint layout can be
achieved using an inexpensive, miniature, non-
shielded, high DCR inductor.
26
2554.2007.01.1.2