AAT3258_06 Datasheet, PDF (2/16 Pages) Advanced Analogic Technologies – 300mA LDO Linear Regulator with μP Reset

AAT3258
300mA LDO Linear Regulator with µP Reset
Pin Descriptions
Pin #
1
Symbol
VIN
2
SHDN
3
VDET
4
MR
5
RESET
6
GND
7
BYP
8
OUT
Function
LDO voltage regulator input pin. This pin should be decoupled with 1µF or
greater capacitor. See application information.
LDO voltage regulator shutdown pin. This pin should not be left floating.
When connected low, all the internal circuitry is powered down. When high, it
is in normal operation.
Microprocessor reset input power supply pin. It may be connected to V_IN.
Manual reset active low input. A logic low signal on MR asserts a reset condi-
tion. Asserted reset continues as long as MR is low and for a minimum of
150ms after MR returns high.
Reset output remains low while V_DET is below the reset threshold and remains
so for a minimum of 150ms after V_DET rises above the reset threshold.
Ground connection pin.
LDO voltage regulator bypass capacitor connection. To improve AC ripple
rejection and decrease LDO regulator self noise, connect a 10nF ceramic
capacitor between this pin and GND.
LDO voltage regulator output pin; should be decoupled with a 2.2µF or
greater value low ESR ceramic capacitor.
Pin Configuration
TSOPJW-8
(Top View)
VIN ¹
SHDN ²
VDET ³
MR ⁴
8 _OUT
7 _BYP
6 _GND
5 _RESET
2
3258.2006.03.1.6