AAT3242_08 Datasheet, PDF (2/15 Pages) Advanced Analogic Technologies – 300mA/150mA Dual CMOS LDO Linear Regulator

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PRODUCT DATASHEET
AAT3242
300mA/150mA Dual CMOS LDO Linear Regulator
Pin Descriptions
Pin #
TSOPJW-12 TDFN33-12
1
12
2, 3, 8, 9
4, 10, EP
4
11
5
9
6
7
7
6
10
5
11
3
12
1
n/a
2, 8
Symbol
ENA
GND
POKA
OUTB
INB
ENB
POKB
OUTA
INA
N/C
Function
Enable Regulator A pin; this pin should not be left floating. When pulled low, the PMOS
pass transistor turns off and the device enters shutdown mode, consuming less than
1μA.
Ground connection pins. For the TDFN33 package, The exposed thermal pad (EP)
should be connected to the board ground plane and Pins 4 and 10. The ground plane
should include a large exposed copper pad under the package with vias to the bottom
layer ground plane for thermal dissipation (see package outline).
Power OK pin with open drain output. It is pulled low when the OUTA pin is below the
10% regulation window.
Low current (150mA) regulator output pin; should be decoupled with a 2.2μF or greater
output low-ESR ceramic capacitor.
Input voltage pin for Regulator B; should be decoupled with 1μF or greater capacitor.
Enable Regulator B; this pin should not be left floating. When pulled low, the PMOS pass
transistor turns off and the device enters shutdown mode, consuming less than 1μA.
Power OK pin with open drain output. It is pulled low when the OUTB pin is below the
10% regulation window.
High-current (300mA) regulator output pin; should be decoupled with a 2.2μF or
greater output low-ESR ceramic capacitor.
Input voltage pin for Regulator A; should be decoupled with 1μF or greater capacitor.
Not connected.
Pin Configuration
TSOPJW-12
(Top View)
TDFN33-12
(Top View)
ENA ¹
GND ²
GND ³
POKA ⁴
OUTB ⁵
INB ⁶
12 _INA
11 _OUTA
10 _POKB
9 _GND
8 _GND
7 _ENB
INA ¹
N/C ²
OUTA ³
GND ⁴
POKB ⁵
ENB ⁶
12 _ENA
11 _POKA
EP
10 _GND
9 _OUTB
8 _N/C
7 _INB
2
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3242.2008.08.1.11