AAT2846 Datasheet, PDF (19/25 Pages) Advanced Analogic Technologies – High Current Charge Pump with Dual LDO for Backlight and Flash Applications

AAT2846
High Current Charge Pump with Dual LDO
for Backlight and Flash Applications
Equivalent Series Resistance
ESR is an important characteristic to consider
when selecting a capacitor. ESR is a resistance
internal to a capacitor that is caused by the leads,
internal connections, size or area, material compo-
sition, and ambient temperature. Capacitor ESR is
typically measured in milliohms for ceramic capac-
itors and can range to more than several ohms for
tantalum or aluminum electrolytic capacitors.
Ceramic Capacitor Materials
Ceramic capacitors less than 0.1µF are typically
made from NPO or C0G materials. NPO and C0G
materials generally have tight tolerance and are
very stable over temperature. Larger capacitor val-
ues are usually composed of X7R, X5R, Z5U, or
Y5V dielectric materials. Large ceramic capacitors
are often available in lower-cost dielectrics, but
capacitors greater than 10µF are not typically
required for AAT2846 applications.
Capacitor area is another contributor to ESR.
Capacitors that are physically larger will have a
lower ESR when compared to an equivalent mate-
rial smaller capacitor. These larger devices can
improve circuit performance when compared to an
equal value capacitor in a smaller package size.
PCB Layout
To achieve adequate electrical and thermal per-
formance, careful attention must be given to the
PCB layout. In the worst-case operating condition,
the chip must dissipate considerable power at full
load. Adequate heat-sinking must be achieved to
ensure intended operation.
Figure 5 illustrates an example PCB layout. The
bottom of the package features an exposed metal
paddle. The exposed paddle acts, thermally, to
transfer heat from the chip and, electrically, as a
ground connection.
The junction-to-ambient thermal resistance (θ_JA) for
the connection can be significantly reduced by fol-
lowing a couple of important PCB design guidelines.
The PCB area directly underneath the package
should be plated so that the exposed paddle can be
mated to the top layer PCB copper during the re-
flow process. Multiple copper plated thru-holes
should be used to electrically and thermally connect
the top surface paddle area to additional ground
plane(s) and/or the bottom layer ground pour.
The chip ground is internally connected to both the
paddle and to the AGND and PGND pins. It is good
practice to connect the GND pins to the exposed
paddle area with traces as shown in the example.
The flying capacitors C1 and C2 should be con-
nected close to the IC. Trace length should be kept
short to minimize path resistance and potential
coupling. The input and output capacitors should
also be placed as close to the chip as possible.
Figure 5: Example PCB Layout.
2846.2007.08.1.0
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