AAT2786 Datasheet, PDF (18/27 Pages) Advanced Analogic Technologies – 1.5A Step-Down Converter and 150mA LDO

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PRODUCT DATASHEET
AAT2786
1.5A Step-Down Converter and 150mA LDO
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current.
V_O
V_IN
· ^⎛⎝1 -
V_O ⎞
V_IN ⎠
=
D · (1 - D) =
0.5² = ¹
2
For V_IN = 2 · V_O
I = _RMS(MAX)
I_O
2
The term
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
appears in both the input voltage
ripple and input capacitor RMS current equations and is
a maximum when V_O is twice V_IN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle.
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the AAT2786. Low
ESR/ESL X7R and X5R ceramic capacitors are ideal for
this function. To minimize stray inductance, the capacitor
should be placed as closely as possible to the IC. This
keeps the high frequency content of the input current
localized, minimizing EMI and input voltage ripple. The
proper placement of the input capacitor (C1) can be seen
in the evaluation board layout in the Layout section of
this datasheet (see Figure 2).
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the evalu-
ation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result. Since the inductance of a
short PCB trace feeding the input voltage is significantly
lower than the power leads from the bench power sup-
ply, most applications do not exhibit this problem.
In applications where the input power source lead induc-
tance cannot be reduced to a level that does not affect
the converter performance, a high ESR tantalum or alu-
minum electrolytic should be placed in parallel with the
low ESR/ESL bypass ceramic capacitor. This dampens
the high Q network and stabilizes the system.
Output Capacitor
The output capacitor limits the output ripple and pro-
vides holdup during large load transitions. A 10μF to
22μF X5R or X7R ceramic capacitor typically provides
sufficient bulk capacitance to stabilize the output during
large load transitions and has the ESR and ESL charac-
teristics necessary for low output ripple.
The output voltage droop due to a load transient is dom-
inated by the capacitance of the ceramic output capacitor.
During a step increase in load current, the ceramic output
capacitor alone supplies the load current until the loop
responds. Within two or three switching cycles, the loop
responds and the inductor current increases to match the
load current demand. The relationship of the output volt-
age droop during the three switching cycles to the output
capacitance can be estimated by:
C_OUT
=
3 · ∆I_LOAD
V_DROOP · F_S
Once the average inductor current increases to the DC
load level, the output voltage recovers. The above equa-
tion establishes a limit on the minimum value for the
output capacitor with respect to load transients.
The internal voltage loop compensation also limits the
minimum output capacitor value to 10μF. This is due to
its effect on the loop crossover frequency (bandwidth),
phase margin, and gain margin. Increased output capac-
itance will reduce the crossover frequency with greater
phase margin.
Adjustable Output Resistor Selection
The output voltage on the AAT2786 is programmed with
external resistors R1 and R2. To limit the bias current
required for the external feedback resistor string while
maintaining good noise immunity, the minimum sug-
gested value for R2 is 59kΩ. Although a larger value will
further reduce quiescent current, it will also increase the
impedance of the feedback node, making it more sensi-
tive to external noise and interference. Table 1 summa-
rizes the resistor values for various output voltages with
R2 set to either 59kΩ for good noise immunity or 221kΩ
for reduced no load input current.
18
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