AAT2846_08 Datasheet, PDF (17/22 Pages) Advanced Analogic Technologies – High Current Charge Pump with Dual LDO for Backlight and Flash Applications

PRODUCT DATASHEET
AAT2846
ChargePump^TM High Current Charge Pump with Dual LDO for Backlight and Flash Applications
The junction-to-ambient thermal resistance (θ_JA) for the
connection can be significantly reduced by following a
couple of important PCB design guidelines.
The PCB area directly underneath the package should be
plated so that the exposed paddle can be mated to the
top layer PCB copper during the re-flow process. Multiple
copper plated thru-holes should be used to electrically
and thermally connect the top surface paddle area to
additional ground plane(s) and/or the bottom layer
ground pour.
The chip ground is internally connected to both the
paddle and to the AGND and PGND pins. It is good prac-
tice to connect the GND pins to the exposed paddle area
with traces as shown in the example.
The flying capacitors C1 and C2 should be connected
close to the IC. Trace length should be kept short to
minimize path resistance and potential coupling. The
input and output capacitors should also be placed as
close to the chip as possible.
Evaluation Board User Interface
The user interface for the AAT2846 evaluation board is
provided through 4 buttons and a number of connection
terminals. The board is operated by supplying external
power and pressing individual buttons or button combi-
nations. The table below indicates the function of each
button or button combination.
To power-on the board, connect a power supply or bat-
tery to the DC- and DC+ terminals. Make the board’s
supply connection by positioning the J1 jumper to the
ON position. A red LED indicates that power is applied.
The evaluation board is made flexible so that the user can
disconnect the enable lines from the microcontroller and
apply external enable signals. By removing the jumpers
from J2, J3, J4 and/or J5, external enable signals can be
applied to the board. External enable signals must be
applied to pin 1 of each J2, J3, J4 or J5 terminal.
When applying external enable signals, consideration
must be given to the voltage levels. The externally
applied voltages cannot exceed the supply voltage that
is applied to the IN pins of the device (DC+).
The LDO loads can be connected directly to the evalua-
tion board. For adequate performance, be sure to con-
nect the load between OUTA/OUTB and DC- as opposed
to some other GND in the system.
Figure 5: Example PCB Layout.
2846.2008.03.1.1
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