AAT2833 Datasheet, PDF (16/20 Pages) Advanced Analogic Technologies – 240mA Total Display Solution for Portable Devices

LED Selection
The AAT2833/34 is designed to drive high-intensity
white LEDs. It is particularly suitable for LEDs with
an operating forward voltage in the range of 4.2V
to 1.5V.
The AAT2833/34 can also drive other loads that
have similar characteristics to white LEDs. For var-
ious load types, the AAT2833/34 provides a high
current, programmable, ideal constant current
channel/sink.
Capacitor Selection
Careful selection of the four external capacitors
C_IN, C1, C2, and C_OUT are important because they
will affect turn-on time, output ripple, and transient
performance. Optimum performance will be
obtained when low equivalent series resistance
(ESR) ceramic capacitors are used. In general, low
ESR is defined as a resistance that is less than
100mΩ.
X7R and X5R ceramic capacitors are highly rec-
ommended over all other types of capacitors for
use with the AAT2833/34. For the input (C_IN) and
output (C_OUT) capacitors, a 2.2µF or greater value
is recommended, and a 1µF or greater value is rec-
ommended for the flying (C1/C2) capacitors.
Ceramic capacitors offer many advantages over
their tantalum and aluminum electrolytic counter-
parts. A ceramic capacitor typically has very low
ESR, is lowest cost, has a smaller PCB footprint,
and is non-polarized. Low ESR ceramic capacitors
help maximize charge pump transient response.
AAT2833/34
240mA Total Display Solution
for Portable Devices
PCB Layout
To achieve adequate electrical and thermal per-
formance, careful attention must be given to the
printed circuit board (PCB) layout. In the worst-case
operating condition, the chip must dissipate consid-
erable power at full load. Adequate heat-sinking
must be achieved to ensure intended operation.
Figures 6 and 7 illustrate an example PCB layout.
The bottom of the package features an exposed
metal pad. The exposed pad acts, thermally, to
transfer heat from the chip and, electrically, as a
ground connection.
The junction-to-ambient thermal resistance (θ_JA) for
the AAT2833/34 package can be significantly
reduced by following a couple of important PCB
design guidelines. The PCB area directly under-
neath the package should be plated so that the
exposed pad can be mated to the top layer PCB
copper during the reflow process. Multiple copper
plated thru-holes should be used to electrically and
thermally connect the AAT2833/34’s exposed pad
area to additional ground plane(s).
The chip ground is internally connected to both the
paddle and to the AGND and PGND pins. It is good
practice to connect the GND pins to the exposed
pad area with traces as shown in Figure 5.
The flying capacitors (C1 and C2), input capacitor
(C4), and output capacitor (C3) should be connect-
ed as close as possible to the IC. In addition to the
external passive components being placed as
close as possible to the IC, all traces connecting
the AAT2833/34 should be as short and wide as
possible to minimize path resistance and potential
coupling.
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2833.2007.09.1.0