AAT2789 Datasheet, PDF (16/22 Pages) Advanced Analogic Technologies – Low Noise, High Frequency Dual Step-Down Converter

SystemPower^TM
PRODUCT DATASHEET
AAT2789
Low Noise, High Frequency Dual Step-Down Converter
V_OUT(V)
0.6
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.8
1.85
2.0
2.5
3.0
3.3
R_{2, 4} = 59kΩ
R_{1, 3}(kΩ)
0
19.6
29.4
39.2
49.9
59.0
68.1
78.7
88.7
118
124
137
187
237
267
R_{2, 4} = 221kΩ
R_{1, 3}(kΩ)
0
75.0
113
150
187
221
261
301
332
442
464
523
715
887
1000
Table 1: AAT2789 Resistor Values for Various
Output Voltages.
Thermal Calculations
There are three types of losses associated with the
AAT2789 step-down converter: switching losses, con-
duction losses, and quiescent current losses. Conduction
losses are associated with the R_DS(ON) characteristics of
the power output switching devices. Switching losses are
dominated by the gate charge of the power output
switching devices. At full load, assuming continuous con-
duction mode (CCM), a simplified form of both step-
down converters is given by:
P_TOTAL
=
I_O12
·
(R_DSON(HS)
·
V_O1
+ R_DSON(L)
V_IN1
·
[V_IN
-V_O1])
+ (t_sw · F_S · I_O1 + I_Q1) · V_IN1
+ ^{IO22 · (RDSON(HS) · VO2 + RDSON(L) · [VIN -VO2])}
V_IN2
+ (t_sw · F_S · I_O2 + I_Q2) · V_IN2
I_Q1 and I_Q2 are the step-down converter quiescent cur-
rents for Channel 1 and Channel 2 respectively. The term
t_SW is used to estimate the full load step-down converter
switching losses.
For the condition where the step-down converter is in
dropout at 100% duty cycle, the total device dissipation
reduces to:
P_TOTAL = I_O12 · R_DS(ON)H1 + I_Q1 · V_IN1 + I_O22 · R_DS(ON)H2 + I_Q2 · V_IN2
Since R_DS(ON), quiescent current, and switching losses all
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range.
Given the total losses, the maximum junction tempera-
ture can be derived from the θ_JA for the TDFN34-16
package, which is 50°C/W.
T_J(MAX) = P_TOTAL · Θ_JA + T_AMB
PCB Layout
The suggested PCB layout for the AAT2789 is shown in
Figures 1 and 2. The following guidelines should be used
to help ensure a proper layout.
1. The input and output capacitors C1, C2, C3, and C4
should be connected as closely as possible to the
input and output pins.
2. Output capacitors and inductors (C2, C3 and L1; C4
and L2) should connect as closely as possible. The
connection of the inductor (L1, L2) to the LX1 and
LX2 pins should be as short as possible.
3. The feedback traces or FB pins should be separated
from any power traces and connect as closely as
possible to the load point. Sensing along a high-
current load trace will degrade DC load regulation.
4. The resistance of the trace from the load return to
PGND should be kept to a minimum. This will help to
minimize any error in DC regulation due to differ-
ences in the potential of the internal signal ground
and the power ground.
5. The lower R2 (FB1) and R4 (FB2) resistor's grounds
should be connected to the AGND1 and AGND2 pins.
6. C5, C6 are optional feed forward capacitors for both
channels to stabilize the output voltage during large
load transitions.
7. For good thermal coupling, PCB vias are required
from the pad for the TDFN paddle to the bottom
ground plane.
16
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2789.2008.03.1.0