AAT2500 Datasheet, PDF (16/26 Pages) Advanced Analogic Technologies – 1MHz Step-Down Converter/LDO Regulator

AAT2500
1MHz Step-Down Converter/LDO Regulator
Manufacturer's specifications list both the inductor
DC current rating, which is a thermal limitation, and
the peak current rating, which is determined by the
saturation characteristics. The inductor should not
show any appreciable saturation under normal load
conditions. Some inductors may meet the peak and
average current ratings yet result in excessive loss-
es due to a high DCR. Always consider the losses
associated with the DCR and its effect on the total
converter efficiency when selecting an inductor.
The 4.7µH CDRH3D16 series inductor selected
from Sumida has a 105mΩ DCR and a 900mA DC
current rating. At full load, the inductor DC loss is
17mW which gives a 2.8% loss in efficiency for a
400mA, 1.5V output.
Input Capacitor
Select a 4.7µF to 10µF X7R or X5R ceramic capac-
itor for the input. To estimate the required input
capacitor size, determine the acceptable input rip-
ple level (V_PP) and solve for C. The calculated
value varies with input voltage and is a maximum
when V_IN is double the output voltage.
V_OBUCK
V_IN
·
⎛⎝₁
-
V_OBUCK⎞
V_IN ⎠
C_IN =
⎛ V_PP
⎝ I_OBUCK
-
ESR^⎞⎠
· F_S
V_OBUCK
V_IN
·
⎛⎝_{1 -}
V_OBUCK⎞
V_IN ⎠
=
1
4
for
V_IN = 2
× V_OBUCK
1
C_IN(MIN) = _{⎛ VPP}
⎝ I_OBUCK
- ESR^⎞⎠ · 4 · F_S
Always examine the ceramic capacitor DC voltage
coefficient characteristics when selecting the prop-
er value. For example, the capacitance of a 10µF,
6.3V, X5R ceramic capacitor with 5.0V DC applied
is actually about 6µF.
The maximum input capacitor RMS current is:
I_RMS = I_OBUCK ·
V_OBUCK
V_IN
·
⎛
⎝
1
-
V_OBUCK⎞
V_IN ⎠
The input capacitor RMS ripple current varies with
the input and output voltage and will always be less
than or equal to half of the total DC load current.
V_OBUCK
V_IN
·
⎛⎝₁
-
V_OBUCK⎞
V_IN ⎠
=
D · (1 - D) =
0.5² = ¹
2
for V_IN = 2 x V_OBUCK
I = _RMS(MAX)
I_OBUCK
2
The term
V_OBUCK
V_IN
·
⎛⎝_{1 -}
V_OBUCK⎞
V_IN ⎠
appears in both the
input voltage ripple and input capacitor RMS cur-
rent equations and is a maximum when V_OBUCK is
twice V_IN. This is why the input voltage ripple and
the input capacitor RMS current ripple are a maxi-
mum at 50% duty cycle.
The input capacitor provides a low impedance loop
for the edges of pulsed current drawn by the
AAT2500. Low ESR/ESL X7R and X5R ceramic
capacitors are ideal for this function. To minimize
stray inductance, the capacitor should be placed as
closely as possible to the IC. This keeps the high
frequency content of the input current localized,
minimizing EMI and input voltage ripple.
The proper placement of the input capacitor (C2)
can be seen in the evaluation board layout in
Figure 3.
A laboratory test set-up typically consists of two
long wires running from the bench power supply to
the evaluation board input voltage pins. The induc-
tance of these wires, along with the low-ESR
ceramic input capacitor, can create a high Q net-
work that may affect converter performance. This
problem often becomes apparent in the form of
excessive ringing in the output voltage during load
transients. Errors in the loop phase and gain meas-
urements can also result.
Since the inductance of a short PCB trace feeding
the input voltage is significantly lower than the
power leads from the bench power supply, most
applications do not exhibit this problem.
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