AAT1270_08 Datasheet, PDF (14/18 Pages) Advanced Analogic Technologies – 1A Step-Up Current Regulator for Flash LEDs

SwitchReg^TM
DC+
DC-
PRODUCT DATASHEET
AAT1270
1A Step-Up Current Regulator for Flash LEDs
JP6
MCU
R5
10K
U2
C4
1μF
EN/SET
1
VDD VSS
8
SW1
2
GP5 GP0
7
0
21
3
GP4 GP1
6
43
5
4
GP3 GP2
5
R7
PIC12F675
330
LED2
GRN
JP7
R8
0
10k
R6
330
LED1
RED
FLEN
0
21
43
5
SW2
JP3
R3
100k
FLINH
0
SW3
21
43
5
JP4
VOUT
R4
100k
(opt)
JP1 JP2
0
0
JP5
EN/SET
R2
100K
L1 1μH
C1
2.2μF
C3
47nF
U1
1 _CT
RSET ¹⁴
2 _ENSET
FLA ¹³
3 _{FLEN FLGND} 12
4 _AGND
FLB ¹¹
5 _IN
FLINH ¹⁰
6 _SW
GND ⁹
7 _PGND
OUT ⁸
AAT1270 STDFN33-14
D1
D2
R1
162k
C2
2.2μF
L1 Murata LQM2HPN1R0MG0 1μH 1.6A 55mΩ
C1, C2 Murata GRM188R71A225KE15 2.2μF 0603 X7R 10V
C3 Murata GRM155R71A473KA01 47nH 0402 X7R 10V
Figure 3: AAT1270 Evaluation Board Schematic.
PCB Layout Guidelines
Boost converter performance can be adversely affected
by poor layout. Possible impact includes high input and
output voltage ripple, poor EMI performance, and
reduced operating efficiency. Every attempt should be
made to optimize the layout in order to minimize para-
sitic PCB effects (stray resistance, capacitance, and
inductance) and EMI coupling from the high frequency
SW node. A suggested PCB layout for the AAT1270 1A
step-up regulator is shown in Figures 4 through 7. The
following PCB layout guidelines should be considered:
1. Minimize the distance from capacitor C_IN and C_OUT’s
negative terminals to the PGND pins. This is espe-
cially true with output capacitor C_OUT, which conducts
high ripple current from the output to the PGND
pins.
2. Minimize the distance between L1 to IN and switch-
ing pin SW; minimize the size of the PCB area con-
nected to the SW pin.
3. Maintain a ground plane and connect to the IC PGND
pin(s) as well as the PGND connections of C_IN and
C_OUT.
4. Consider additional PCB exposed area for the flash
LEDs to maximize heatsinking capability. This may
be necessary when using high current application
and long flash duration application.
5. Connect the exposed paddle (bottom of the die) to
either PGND or GND. Connect AGND, FLGND to GND
as close as possible to the package.
14
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1270.2008.07.1.5