AAT3215 Datasheet, PDF (13/16 Pages) Advanced Analogic Technologies – 150mA CMOS High Performance LDO

AAT3215
150mA CMOS High Performance LDO
Applications Information
V_IN
IIN
DC INPUT
GND
VIN
LDO ^VOUT
Regulator
EN
BYP
GND
C_IN
I_RIPPLE
I_GND
I_BYP + noise
I_LOAD
C_BYP
GND
LOOP
C_BYP
R_TRACE
R_TRACE
I_LOAD return + noise and ripple
R_TRACE
C_OUT
R_TRACE
R_LOAD
Figure 1: Common LDO Regulator Layout with C_BYP Ripple feedback loop
Figure 2 shows the preferred method for the bypass
and output capacitor connections. For low output
noise and highest possible power supply ripple
rejection performance, it is critical to connect the
bypass and output capacitor directly to the LDO reg-
ulator ground pin. This method will eliminate any
load noise or ripple current feedback through the
LDO regulator.
IIN
V_IN
DC INPUT
GND
I_LOAD
V_IN
LDO ^VOUT
Regulator
EN
BYP
GND
C_IN
I_RIPPLE
I_GND
I_BYP only
C_BYP
R_TRACE
R_TRACE
I_LOAD return + noise and ripple
R_TRACE
C_OUT
R_TRACE
R_LOAD
Figure 2: Recommended LDO Regulator Layout
Evaluation Board Layout
The AAT3215 evaluation layout follows the recom-
mend printed circuit board layout procedures and
can be used as an example for good application
layouts.
Note: Board layout shown is not to scale.
Figure 3: Evaluation board
component side layout
3215.2002.03.0.91
Figure 4: Evaluation board
solder side layout
Figure 5: Evaluation board
top side silk screen layout /
assembly drawing
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