AAT3174 Datasheet, PDF (13/14 Pages) Advanced Analogic Technologies – High Current, High Efficiency Charge Pump

AAT3174
High Current, High Efficiency Charge Pump
itors and can range to more than several ohms for
tantalum or aluminum electrolytic capacitors.
Ceramic Capacitor Materials
Ceramic capacitors less than 0.1µF are typically
made from NPO or C0G materials. NPO and C0G
materials generally have tight tolerance and are
very stable over temperature. Larger capacitor val-
ues are usually composed of X7R, X5R, Z5U, or
Y5V dielectric materials. Large ceramic capacitors
are often available in lower-cost dielectrics, but
capacitors greater than 4.7µF are not typically
required for AAT3174 applications.
Capacitor area is another contributor to ESR.
Capacitors that are physically large will have a lower
ESR when compared to an equivalent material
smaller capacitor. These larger devices can improve
circuit transient response when compared to an
equal value capacitor in a smaller package size.
Thermal Protection
The AAT3174 has a thermal protection circuit that
will shut down the charge pump if the die tempera-
ture rises above the thermal limit, as is the case
during a short-circuit of the OUT pin.
PCB Layout
To achieve adequate electrical and thermal per-
formance, careful attention must be given to the
PCB layout. In the worst-case operating condition,
the chip must dissipate considerable power at full
load. Adequate heat-sinking must be achieved to
ensure intended operation.
Figure 2 illustrates an example of an adequate
PCB layout. The bottom of the package features an
exposed metal paddle. The exposed paddle acts,
thermally, to transfer heat from the chip and, elec-
trically, as a ground connection.
The junction-to-ambient thermal resistance (θ_JA) for
the package can be significantly reduced by follow-
ing a couple of important PCB design guidelines.
The PCB area directly underneath the package
should be plated so that the exposed paddle can
be mated to the top layer PCB copper during the
re-flow process. This area should also be connect-
ed to the top layer ground pour when available.
Further, multiple copper plated thru-holes should
be used to electrically and thermally connect the
top surface paddle area to additional ground
plane(s) and/or the bottom layer ground pour.
The chip ground is internally connected to both the
paddle and the GND pin. The GND pin conducts
large currents and it is important to minimize any
differences in potential that can result between the
GND pin and exposed paddle. It is good practice to
connect the GND pin to the exposed paddle area
using a trace as shown in Figure 2.
Figure 2: Example PCB Layout.
The flying capacitors C1 and C2 should be con-
nected close to the chip. Trace length should be
kept short to minimize path resistance and potential
coupling. The input and output capacitors should
also be placed as close to the chip as possible.
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