AAT3170_08 Datasheet, PDF (13/15 Pages) Advanced Analogic Technologies – High Current LED Flash Driver Charge Pump IC

ChargePump^TM
PRODUCT DATASHEET
AAT3170
High Current LED Flash Driver Charge Pump IC
Ceramic Capacitor Materials
Ceramic capacitors less than 0.1μF are typically made
from NPO or C0G materials. NPO and C0G materials
typically have tight tolerance and are stable over tem-
perature. Large capacitor values are typically composed
of X7R, X5R, Z5U, or Y5V dielectric materials. Large
ceramic capacitors are often available in lower-cost
dielectrics, but capacitors greater than 4.7μF are not
typically required for AAT3170 applications.
Capacitor area is another contributor to ESR. Capacitors
that are physically large will have a lower ESR when
compared to an equivalent material, smaller capacitor.
These larger devices can improve circuit transient
response when compared to an equal value capacitor in
a smaller package size.
PCB Layout
To achieve adequate electrical and thermal performance,
careful attention must be given to the PCB layout. In the
worst-case operating condition, the chip must dissipate
considerable power at full load. Adequate heat-sinking
must be achieved to ensure intended operation.
Figure 3 illustrates an example of an adequate PCB lay-
out. The bottom of the package features an exposed
metal paddle. The exposed paddle acts, thermally, to
transfer heat from the chip and, electrically, as a ground
connection.
The junction-to-ambient thermal resistance (θ_JA) for the
package can be significantly reduced by following a
couple of important PCB design guidelines.
The PCB area directly underneath the package should be
plated so that the exposed paddle can be mated to the
top layer PCB copper during the re-flow process. This
area should also be connected to the top layer ground
pour when available. Further, multiple copper plated
thru-holes should be used to electrically and thermally
connect the top surface paddle area to additional ground
plane(s) and/or the bottom layer ground pour.
The chip ground is internally connected to both the
paddle and the GND pin. The GND pin conducts large
currents and it is important to minimize any differences
in potential that can result between the GND pin and
exposed paddle. It is good practice to connect the GND
pin to the exposed paddle area using a trace as shown
in Figure 3.
The flying capacitors C1 and C2 should be connected
close to the chip. Trace length should be kept short to
minimize path resistance and potential coupling. The
input and output capacitors should also be placed as
close to the chip as possible.
Figure 3: Example PCB Layout.
3170.2007.11.1.2
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