AAT2856_08 Datasheet, PDF (13/18 Pages) Advanced Analogic Technologies – High Current Charge Pump with Dual LDO for Backlight Applications

PRODUCT DATASHEET
AAT2856
ChargePump^TM High Current Charge Pump with Dual LDO for Backlight Applications
Similarly, when the input falls further, such that 1.5X
mode can no longer sustain LED drive current, the device
will automatically switch to 2X mode. In 2X mode, the
output voltage can be boosted to twice the input voltage.
The doubling conversion ratio introduces a corresponding
doubling of the input current. For ideal conversion, the
2X mode efficiency is given by:
η=
V_F · I_LED
V_IN · 2I_IN
=
V_F
2 · V_IN
LED Selection
The AAT2856 is designed to drive high-intensity white
LEDs. It is particularly suitable for LEDs with an operat-
ing forward voltage in the range of 1.5V to 4.2V.
The charge pump can also drive other loads that have
similar characteristics to white LEDs. For various load
types, the AAT2856 provides a high-current, program-
mable ideal constant current source.
Capacitor Selection
Careful selection of the four external capacitors C_IN, C₁,
C₂, and C_OUT is important because they will affect turn-on
time, output ripple, and transient performance. Optimum
performance will be obtained when low equivalent series
resistance (ESR) ceramic capacitors are used. In gen-
eral, low ESR may be defined as less than 100mΩ.
Ceramic composition capacitors are highly recommend-
ed over all other types of capacitors for use with the
AAT2856. Ceramic capacitors offer many advantages
over their tantalum and aluminum electrolytic counter-
parts. A ceramic capacitor typically has very low ESR, is
lowest cost, has a smaller PCB footprint, and is non-
polarized. Low ESR ceramic capacitors help maximize
charge pump transient response. Since ceramic capaci-
tors are non-polarized, they are not prone to incorrect
connection damage.
Equivalent Series Resistance
ESR is an important characteristic to consider when
selecting a capacitor. ESR is a resistance internal to a
capacitor that is caused by the leads, internal connec-
tions, size or area, material composition, and ambient
temperature. Capacitor ESR is typically measured in mil-
liohms for ceramic capacitors and can range to more
than several ohms for tantalum or aluminum electrolytic
capacitors.
Ceramic Capacitor Materials
Ceramic capacitors less than 0.1μF are typically made
from NPO or C0G materials. NPO and C0G materials
generally have tight tolerance and are very stable over
temperature. Larger capacitor values are usually com-
posed of X7R, X5R, Z5U, or Y5V dielectric materials.
Large ceramic capacitors are often available in lower-
cost dielectrics, but capacitors greater than 10μF are not
typically required for AAT2856 applications.
Capacitor area is another contributor to ESR. Capacitors
that are physically larger will have a lower ESR when
compared to an equivalent material smaller capacitor.
These larger devices can improve circuit performance
when compared to an equal value capacitor in a smaller
package size.
PCB Layout
To achieve adequate electrical and thermal performance,
careful attention must be given to the PCB layout. In the
worst-case operating condition, the chip must dissipate
considerable power at full load. Adequate heat-sinking
must be achieved to ensure intended operation.
Figure 3 illustrates an example PCB layout. The bottom
of the package features an exposed metal paddle. The
exposed paddle acts, thermally, to transfer heat from
the chip and, electrically, as a ground connection.
The junction-to-ambient thermal resistance (θ_JA) for the
connection can be significantly reduced by following a
couple of important PCB design guidelines.
The PCB area directly underneath the package should be
plated so that the exposed paddle can be mated to the
top layer PCB copper during the re-flow process. Multiple
copper plated thru-holes should be used to electrically
and thermally connect the top surface paddle area to
additional ground plane(s) and/or the bottom layer
ground pour.
The chip ground is internally connected to both the
paddle and to the AGND and PGND pins. It is good prac-
tice to connect the GND pins to the exposed paddle area
with traces as shown in the example.
The flying capacitors C1 and C2 should be connected
close to the IC. Trace length should be kept short to
minimize path resistance and potential coupling. The
input and output capacitors should also be placed as
close to the chip as possible.
2856.2008.02.1.3
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