AAT2510 Datasheet, PDF (13/20 Pages) Advanced Analogic Technologies – Dual 400mA, 1MHz Step-Down DC-DC Converter

AAT2510
Dual 400mA, 1MHz Step-Down DC-DC Converter
Thermal Calculations
There are three types of losses associated with the
AAT2510 converter: switching losses, conduction
losses, and quiescent current losses. Conduction
losses are associated with the R_DS(ON) characteristics
of the power output switching devices. Switching
losses are dominated by the gate charge of the
power output switching devices. At full load, assum-
ing continuous conduction mode (CCM), a simplified
form of the dual converter losses is given by:
P_TOTAL
=
I_O12
·
(R_DSON(HS)
·
V_O1
+ R_DSON(LS)
V_IN
·
[V_IN
-V_O1])
+ ^{IO22 · (RDSON(HS) · VO2 + RDSON(LS) · [VIN -VO2])}
V_IN
+ (t_sw · F · [I_O1 + I_O2] + 2 · I_Q) · V_IN
I_Q is the AAT2510 quiescent current for one chan-
nel and t_sw is used to estimate the full load switch-
ing losses.
For the condition where channel one is in dropout
at 100% duty cycle, the total device dissipation
reduces to:
P_TOTAL = I_O12 · R_DSON(HS)
+ ^{IO22 · (RDSON(HS) · VO2 + RDSON(LS) · [VIN -VO2])}
V_IN
+ (t_sw · F · I_O2 + 2 · I_Q) · V_IN
Since R_DS(ON), quiescent current, and switching
losses all vary with input voltage, the total losses
should be investigated over the complete input
voltage range.
Given the total losses, the maximum junction tem-
perature can be derived from the θ_JA for the
TDFN33-12 package which is 50°C/W.
T_J(MAX) = P_TOTAL • Θ_JA + T_AMB
PCB Layout
The following guidelines should be used to insure a
proper layout.
1. Due to the pin placement of V_IN for both con-
verters, proper decoupling is not possible with
just one input capacitor. The large input capaci-
tor C3 should connect as closely as possible to
V_P and GND, as shown in Figure 4. The addi-
tional input bypass capacitor C8 is necessary for
proper high frequency decoupling of the second
converter.
2. The output capacitor and inductor should be
connected as closely as possible. The connec-
tion of the inductor to the LX pin should also be
as short as possible.
3. The feedback trace should be separate from any
power trace and connect as closely as possible
to the load point. Sensing along a high-current
load trace will degrade DC load regulation. If
external feedback resistors are used, they
should be placed as closely as possible to the
FB pin. This prevents noise from being coupled
into the high impedance feedback node.
4. The resistance of the trace from the load return
to GND should be kept to a minimum. This will
help to minimize any error in DC regulation due
to differences in the potential of the internal sig-
nal ground and the power ground.
5. For good thermal coupling, PCB vias are required
from the pad for the TDFN paddle to the ground
plane. The via diameter should be 0.3mm to
0.33mm and positioned on a 1.2 mm grid.
2510.2005.08.1.5
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