AAT4280A_08 Datasheet, PDF (12/16 Pages) Advanced Analogic Technologies – Slew Rate Controlled Load Switch

SmartSwitch^TM
For example, if V_IN = 5V, R_DS(MAX) = 154mΩ and T_A =
25°C, I_OUT(MAX) = 2.3A. If the output load current were to
exceed 2.3A or if the ambient temperature were to
increase, the internal die temperature would increase
and the device would be damaged.
Higher peak currents can be obtained with the AAT4280A.
To accomplish this, the device thermal resistance must
be reduced by increasing the heat sink area or by oper-
ating the load switch in a duty-cycle manner.
High Peak Output Current Applications
Some applications require the load switch to operate at
a continuous nominal current level with short duration,
high-current peaks. The duty cycle for both output cur-
rent levels must be taken into account. To do so, first
calculate the power dissipation at the nominal continu-
ous current level, and then add in the additional power
dissipation due to the short duration, high-current peak
scaled by the duty factor.
For example, a 4V system using an AAT4280A operates
at a continuous 100mA load current level and has short
2A current peaks, as in a GSM application. The current
peak occurs for 576μs out of a 4.61ms period.
First, the current duty cycle is calculated:
% Peak Duty Cycle: X/100 = 576μs/4.61ms
% Peak Duty Cycle = 12.5%
The load current is 100mA for 87.5% of the 4.61ms
period and 2A for 12.5% of the period. Since the
Electrical Characteristics do not report R_DS(MAX) for 4V
operation, it must be calculated approximately by con-
sulting the chart of R_DS(ON) vs. V_IN. The R_DS reported for
5V can be scaled by the ratio seen in the chart to derive
the R_DS for a 4V V_IN: 120mΩ · 87mΩ /80mΩ = 130mΩ.
De-rated for temperature: 130mΩ · (1 + 0.0028 · (125°C
- 25°C)) = 166mΩ. The power dissipation for a 100mA
load is calculated as follows:
P_D(MAX) = I_OUT2 · R_DS
P_D(100mA) = (100mA)² · 166mW
P_D(100mA) = 1.66mW
P_D(87.5%D/C) = %DC · P_D(100mA)
P_D(87.5%D/C) = 0.875 · 1.66mW
P_D(87.5%D/C) = 1.45mW
PRODUCT DATASHEET
AAT4280A
Slew Rate Controlled Load Switch
The power dissipation for 100mA load at 87.5% duty
cycle is 1.45mW. Now the power dissipation for the
remaining 12.5% of the duty cycle at 2A is calculated:
P_D(MAX) = I_OUT2 · R_DS
P_D(2A) = (2A)² · 166mΩ
P_D(2A) = 664mW
P_D(12.5%D/C) = %DC · P_D(2A)
P_D(12.5%D/C) = 0.125 · 664mΩ
P_D(12.5%D/C) = 83mW
The power dissipation for 2A load at 12.5% duty cycle is
83mW. Finally, the two power figures are summed to
determine the total true power dissipation under the
varied load:
P_D(total) = P_D(100mA) + P_D(2A)
P_D(total) = 1.45mW + 83mW
P_D(total) = 84.5mW
The maximum power dissipation for the AAT4280A oper-
ating at an ambient temperature of 85°C is 333mW. The
device in this example will have a total power dissipation
of 84.5mW. This is well within the thermal limits for safe
operation of the device; in fact, at 85°C, the AAT4280A
will handle a 2A pulse for up to 50% duty cycle. At lower
ambient temperatures, the duty cycle can be further
increased.
Printed Circuit Board
Layout Recommendations
For proper thermal management and to take advantage
of the low R_DS(ON) of the AAT4280A, a few circuit board
layout rules should be followed: V_IN and V_OUT should be
routed using wider than normal traces, and GND should
be connected to a ground plane. To maximize package
thermal dispation and power handling capacity of the
AAT4280A SC70JW-8 package, the ground plane area
connected to the ground pins should be made as large
as possible. For best performance, C_IN and C_OUT should
be placed close to the package pins.
Evaluation Board Layout
The AAT4280A evaluation layout follows the printed cir-
cuit board layout recommendations and can be used for
good applications layout. Refer to Figures 1 through 3.
Note: Board layout shown is not to scale.
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4280A.2008.04.1.5