AAT3177 Datasheet, PDF (12/16 Pages) Advanced Analogic Technologies – High Current, High Efficiency Charge Pump with Auto-Timer

ChargePump^TM
PRODUCT DATASHEET
AAT3177
High Current, High Efficiency Charge Pump with Auto-Timer
Capacitor Selection
Careful selection of the four external capacitors C_IN, C₁,
C₂, and C_OUT is important because they will affect turn-on
time, output ripple, and transient performance. Optimum
performance will be obtained when low equivalent series
resistance (ESR) ceramic capacitors are used. In gener-
al, low ESR may be defined as less than 100mΩ. A value
of 1μF for the flying capacitors is a good starting point
when choosing capacitors. If the LED current sinks are
only programmed for light current levels, then the
capacitor size may be decreased.
Ceramic composition capacitors are highly recommend-
ed over all other types of capacitors for use with the
AAT3177. Ceramic capacitors offer many advantages
over their tantalum and aluminum electrolytic counter-
parts. A ceramic capacitor typically has very low ESR, is
lowest cost, has a smaller PCB footprint, and is non-
polarized. Low ESR ceramic capacitors help maximize
charge pump transient response. Since ceramic capaci-
tors are non-polarized, they are not prone to incorrect
connection damage.
Equivalent Series Resistance
ESR is an important characteristic to consider when
selecting a capacitor. ESR is a resistance internal to a
capacitor that is caused by the leads, internal connec-
tions, size or area, material composition, and ambient
temperature. Capacitor ESR is typically measured in mil-
liohms for ceramic capacitors and can range to more
than several ohms for tantalum or aluminum electrolytic
capacitors.
Ceramic Capacitor Materials
Ceramic capacitors less than 0.1μF are typically made
from NPO or C0G materials. NPO and C0G materials gen-
erally have tight tolerance and are very stable over tem-
perature. Larger capacitor values are usually composed
of X7R, X5R, Z5U, or Y5V dielectric materials. Large
ceramic capacitors are often available in lower-cost
dielectrics, but capacitors greater than 4.7μF are not
typically required for AAT3177 applications.
Capacitor area is another contributor to ESR. Capacitors
that are physically large will have a lower ESR when
compared to an equivalent material smaller capacitor.
These larger devices can improve circuit transient
response when compared to an equal value capacitor in
a smaller package size.
Thermal Protection
The AAT3177 has a thermal protection circuit that will
shut down the charge pump if the die temperature rises
above the thermal limit, as is the case during a short-
circuit of the OUT pin.
PCB Layout
To achieve adequate electrical and thermal performance,
careful attention must be given to the PCB layout. In the
worst-case operating condition, the chip must dissipate
considerable power at full load. Adequate heat-sinking
must be achieved to ensure intended operation.
Figure 4 illustrates an example of an adequate PCB lay-
out. The bottom of the package features an exposed
metal paddle. The exposed paddle acts, thermally, to
transfer heat from the chip and, electrically, as a ground
connection.
The junction-to-ambient thermal resistance (θ_JA) for the
package can be significantly reduced by following a
couple of important PCB design guidelines.
The PCB area directly underneath the package should be
plated so that the exposed paddle can be mated to the
top layer PCB copper during the re-flow process. This
area should also be connected to the top layer ground
pour when available. Further, multiple copper plated
thru-holes should be used to electrically and thermally
connect the top surface paddle area to additional ground
plane(s) and/or the bottom layer ground pour.
The chip ground is internally connected to both the paddle
and the GND pin. The GND pin conducts large currents
and it is important to minimize any differences in potential
that can result between the GND pin and exposed paddle.
It is good practice to connect the GND pin to the exposed
paddle area using a trace as shown in Figure 4.
The flying capacitors C1 and C2 should be connected
close to the chip. Trace length should be kept short to
minimize path resistance and potential coupling. The
input and output capacitors should also be placed as
close to the chip as possible.
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3177.2008.06.1.0