AAT1150_06 Datasheet, PDF (12/17 Pages) Advanced Analogic Technologies – 1MHz 1A Step-Down DC/DC Converter

AAT1150
1MHz 1A Step-Down DC/DC Converter
current varies with the input voltage and the output
voltage. The equation for the RMS current in the
input capacitor is:
I_RMS = I_O ⋅
V_O
V_IN
⋅ _⎝⎛1 -
V_O ⎞
V_IN ⎠
The input capacitor RMS ripple current reaches a
maximum when V_IN is two times the output voltage
where it is approximately one half of the load cur-
rent. Losses associated with the input ceramic
capacitor are typically minimal and are not an
issue. Proper placement of the input capacitor can
be seen in the reference design layout shown in
Figures 4 and 5.
Output Capacitor
Since there are no external compensation compo-
nents, the output capacitor has a strong effect on
loop stability. Larger output capacitance will
reduce the crossover frequency with greater phase
margin. For the 1.5V 1.0A design using the 4.1μH
inductor, three 22μF 6.3V X5R capacitors provide a
stable output. In addition to assisting stability, the
output capacitor limits the output ripple and pro-
vides holdup during large load transitions.
The output capacitor RMS ripple current is given by:
1
I_RMS
=
2
⋅
⋅ ^{VOUT ⋅ (VIN - VOUT)}
3
L ⋅ F_S ⋅ V_IN
For a ceramic capacitor, the dissipation due to the
RMS current of the capacitor is not a concern.
Tantalum capacitors, with sufficiently low ESR to
meet output voltage ripple requirements, also have
an RMS current rating much greater than that actu-
ally seen in this application.
Adjustable Output
For applications requiring an output other than the
fixed outputs available, the 1V version can be pro-
grammed externally (see Figure 6). Resistors R3
and R4 force the output to regulate higher than
1V. R4 should be 100 times less than the internal
1mΩ resistance of the FB pin. Once R4 is selected,
R3 can be calculated. For a 1.25V output with R4
set to 10kΩ, R3 is 2.55kΩ.
R3 = (V_O - 1) ⋅ R4 = 0.25 ⋅ 10.0kΩ = 2.55kΩ
Layout Considerations
Figures 4 and 5 display the suggested PCB layout
for the AAT1150. The most critical aspect of the lay-
out is the placement of the input capacitor C1. For
proper operation, C1 must be placed as closely as
possible to the AAT1150.
Thermal Calculations
There are two types of losses associated with the
AAT1150 output switching MOSFET: switching
losses and conduction losses. Conduction losses
are associated with the R_DS(ON) characteristics of
the output switching device. At full load, assuming
continuous conduction mode (CCM), a simplified
form of the total losses is:
P_LOSS
= ^{IO2 ⋅ (RDS(ON)H ⋅ VO + RDS(ON)L â‹}
V_IN
(V_IN - V_O))
+ t_sw ⋅ F_S ⋅ I_O ⋅ V_IN + I_Q ⋅ V_IN
Once the total losses have been determined, the
junction temperature can be derived from the Θ_JA
for the MSOP-8 package.
12
1150.2006.09.1.5