AAT1142 Datasheet, PDF (12/22 Pages) Advanced Analogic Technologies – 800mA Voltage-Scaling Step-Down Converter

AAT1142
800mA Voltage-Scaling Step-Down Converter
V_OUT
1
2
JP1
LX
C4
(optional)
0.1µF
C2
10µF
L1
2.2µH
V_IN
V_IN
(optional)
R5
1.8K
SDA
1
SCL
2
JP2
R4
1.8K
U1
1 _LX
VIN ¹²
2 _PGND
AGND ¹¹
3 _{MODE/SYNC AGND} 10
4 _SDA
AGND ⁹
5 _SCL
AGND ⁸
6 _EN/SET
FB ⁷
AAT1142
V_IN
TSOPJW-12
U1 AAT1142 TSOPJW-12
L1 CDRH2D14/2R2
C1 4.7µF 10V 0805 X5R
C2 10µF 10V 0805 X5R
C3 10µF optional
C4 0.1µF optional
R1 0Ω 0603
R2 optional 0603
R3 10K 0603
R4, R5 1.8K 0603
V_IN
C1
4.7µF
V_IN
C3
(optional)
10µF
R1
0
R3
10K
1
2
3
JP3
R2
(optional)
Figure 1: AAT1142 Evaluation Board Schematic.
Applications Information
The AAT1142 output voltage may be programmed
from 0.6V to 2.0V through I²C or S²Cwire serial
interface. When using I²C or S²Cwire, the output
voltage can be programmed across the entire out-
put voltage range or in increments as small as
±50mV (see Figure 2).
I²C Serial Interface
The AAT1142 is compatible with the I²C interface,
which is a widely used two-line serial interface.
The I²C two-wire communications bus consists of
SDA and SCL lines. SDA provides data, while SCL
provides clock input. SDA data consists of an
address bit sequence followed by a data bit
sequence. SDA data transfer is synchronized to
SCL rising clock edges.
When using the I²C interface, EN/SET is pulled
high to enable the output or low to disable the out-
put. To ensure a disable event, the EN/SET pulse
width must be greater than the latch time (500µs
maximum).
The I²C serial interface requires a master to initiate
all the communications with slave devices. The I²C
protocol is a bidirectional bus allowing both read and
write actions to take place; while the AAT1142 is a
slave device and only supports the write protocol.
The AAT1142 is a receiver-only (or write-only)
slave device and the Read / Write (R/W) bit is set
low. The AAT1142 address is preset to 0x14 (Hex).
I²C START and STOP Conditions
START and STOP conditions are initialized by the
I²C bus master. The master determines the START
(beginning) and STOP (end) of a transfer with the
slave device. Prior to initiating a START or after
STOP, both the SDA and SCL lines are in bus-free
mode. Bus-free mode is when SDA and SCL are
both in the high state (see Figure 3).
12
1142.2006.07.1.0