AAT1121 Datasheet, PDF (11/20 Pages) Advanced Analogic Technologies – 1.5MHz, 250mA Step-Down Converter

AAT1121
1.5MHz, 250mA Step-Down Converter
Output Voltage (V)
1.0
1.2
1.5
1.8
2.5
3.0
3.3
L1 (μH)
1.5
2.2
2.7
3.0
3.9
4.7
5.6
Table 1: Inductor Values.
The 3.0μH CDRH2D09 series inductor selected
from Sumida has a 150mΩ DCR and a 470mA DC
current rating. At full load, the inductor DC loss is
9.375mW which gives a 2.08% loss in efficiency for
a 250mA, 1.8V output.
Input Capacitor
Select a 4.7μF to 10μF X7R or X5R ceramic capac-
itor for the input. To estimate the required input
capacitor size, determine the acceptable input rip-
ple level (V_PP) and solve for C_IN. The calculated
value varies with input voltage and is a maximum
when V_IN is double the output voltage.
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
C_IN =
⎛ V_PP
⎝ I_O
- ESR^⎞⎠ · F_S
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
=
1
4
for
V_IN
=
2
×
V_O
1
C_IN(MIN) = _{⎛ VPP}
⎝ I_O
- ESR^⎞⎠ · 4 · F_S
Always examine the ceramic capacitor DC voltage
coefficient characteristics when selecting the prop-
er value. For example, the capacitance of a 10μF,
6.3V, X5R ceramic capacitor with 5.0V DC applied
is actually about 6μF.
The maximum input capacitor RMS current is:
I_RMS = I_O ·
V_{O ·} ⎛_{1 -} V_O ⎞
V_IN ⎝ V_IN ⎠
1121.2006.04.1.0
The input capacitor RMS ripple current varies with
the input and output voltage and will always be less
than or equal to half of the total DC load current.
V_O
V_IN
· ^⎛⎝1 -
V_O ⎞
V_IN ⎠
=
D · (1 - D) =
0.5² = ¹
2
for V_IN = 2 x V_O
I = _RMS(MAX)
I_O
2
The term
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
appears in both the input
voltage ripple and input capacitor RMS current
equations and is a maximum when V_O is twice V_IN.
This is why the input voltage ripple and the input
capacitor RMS current ripple are a maximum at
50% duty cycle.
The input capacitor provides a low impedance loop
for the edges of pulsed current drawn by the
AAT1121. Low ESR/ESL X7R and X5R ceramic
capacitors are ideal for this function. To minimize
stray inductance, the capacitor should be placed as
closely as possible to the IC. This keeps the high
frequency content of the input current localized,
minimizing EMI and input voltage ripple.
The proper placement of the input capacitor (C1)
can be seen in the evaluation board layout in
Figure 2.
A laboratory test set-up typically consists of two
long wires running from the bench power supply to
the evaluation board input voltage pins. The induc-
tance of these wires, along with the low-ESR
ceramic input capacitor, can create a high Q net-
work that may affect converter performance. This
problem often becomes apparent in the form of
excessive ringing in the output voltage during load
transients. Errors in the loop phase and gain meas-
urements can also result.
Since the inductance of a short PCB trace feeding
the input voltage is significantly lower than the
power leads from the bench power supply, most
applications do not exhibit this problem.
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