RFSP5032 Datasheet, PDF (2/12 Pages) ANADIGICS, Inc – 5 GHz 802.11a WLAN Power Amplifier

RFS P5032
PIN
1
2
3
4
5
6
7,8,9
10
11
12
NAME
GND
RFIN
GND
VPC1
GND
VPC2
RFOUT
VCC
VCC2
VCC3
Table 1: Pin Description
DESCRIPTION
Ground. Connect directly to PCB ground pattern under IC using the shortest possible
path.
RF Input. RF input to power amplifier matched to 50 V. Route as coplanar waveguide
using adjacent ground pins. RF input can be optimally impedance matched with shunt
capacitor. Application circuit shows stub capacitor.
Ground. Connect directly to PCB ground pattern under IC using the shortest possible
path.
Power Control. Power amplifier bias control pin for stage 1. The recommended use is for
on/off control of the PA. Nominally, 0 V applied will turn amplifier completely off; +3.3 V
should be used to set amplifier to maximum output capability. At maximum output power
capability, this pin will draw approximately 1 to 2 mA of current. A series resistor is used
to set the current flow into the pin, thereby controlling the overall bias level of the PA.
Ground. Connect directly to PCB ground pattern under IC using the shortest possible
path.
Power Control. Power amplifier bias control pin for stage 2. The recommended use is for
on/off control of the PA. Nominally, 0 V applied will turn amplifier completely off; +3.3 V
should be used to set amplifier to maximum output capability. At maximum output power
capability, this pin will draw as much as 1 to 2 mA of current. A series resistor is used to
set the current flow into the pin, therefore setting overall bias level of the PA.
RF Output. RF output of power amplifier can be optimally impedance matched with
additional shunt capacitor enabling maximum linearity. Application circuit shows stub
capacitor. This pin is also used to bias the 3rd stage power transistor through an RF
choke inductor.
Supply Voltage. Main Bias feed for bias control circuitry on all stages.
Supply Voltage. Bias for power transistor of stage 2. Typically set to +3.3 V.
Supply Voltage. Bias for power transistor of stage 1. Typically set to +3.3 V.
2
PRELIMINARY DATA SHEET - Rev 1.4
04/2006