ARA2000 Datasheet, PDF (12/20 Pages) ANADIGICS, Inc – Address-Programmable Reverse Amplifier with Step Attenuator

ARA2000
LOGIC PROGRAMMING
Programming Instructions
The programming word is set through a 16 bit shift
register via the data, clock and enable lines. The
data is entered in order with the most significant bit
(MSB) first and the least significant bit (LSB) last.
The enable line must be low for the duration of the
data entry, then set high to latch the shift register.
The rising edge of the clock pulse shifts each data
value into the register.
Table 6: Programming Word
DATA BIT D₁₅ D₁₄ D₁₃ D₁₂ D₁₁ D₁₀ D₉ D₈ D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀
Value
P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 1 C1 C0 1 1
Table 7: Data Description
VALUE
FUNCTION
(1 = on, 0 = bypass)
P7
N/A
P6
N/A
P5
32 dB Attenuator Bit
P4
16 dB Attenuator Bit
P3
8 dB Attenuator Bit
P2
4 dB Attenuator Bit
P1
2 dB Attenuator Bit
P0
1 dB Attenuator Bit
Table 8: Device Address
LOGIC LEVEL INPUT TO
ADDRESS DEVICE
C1
C0 Pin 16 (C1) Pin 15 (C0)
0
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
The device is selected when the logic inputs at pins
16 and 15 match the values of data bits C1 and C0,
respectively.
DATA
D₁₅: MSB
D₁₄
CLOCK
D₈
D₇
D₁
D₀: LSB
ENABLE
OR
ENABLE
12
Figure 17: Serial Data Input Timing
Data Sheet - Rev 2.2
06/2004