AWC6323 Datasheet, PDF (1/11 Pages) ANADIGICS, Inc – HELP3ETM Dual-band Cellular & PCS CDMA 3.4 V Linear Power Amplifier Module

AWC6323
HELP3E^TM Dual-band Cellular & PCS CDMA
FEATURES
• InGaP HBT Technology
3.4 V Linear Power Amplifier Module
Data Sheet - Rev 2.2
• High Efficiency (Cell Band):
• 37.5 % @ POUT = +27.6 dBm
• 23 % @ POUT = +16 dBm
• 11.5 % @ POUT = +10 dBm
• Low Quiescent Current: 3.5 mA
• Internal Voltage Regulation
AWC6323
• Built-in Directional Coupler
• Common VMODE Control Line
• Simplified VCC Bus PCB routing
• Reduced External Component Count
• Low Profile Surface Mount Package: 1 mm
• RoHS Compliant Package, 260 ^oC MSL-3
APPLICATIONS
• Cell & PCS Dual-band Wireless Handsets and
Data Devices for CDMA/EVDO networks.
M47 Package
14 Pin 3 mm x 5 mm x 1 mm
Surface Mount Module
PRODUCT DESCRIPTION
AWC6323 addresses the demand for increased
integration in dual-band handsets for CDMA networks.
The small footprint 3 mm x 5 mm x 1 mm surface-
mount RoHS compliant package contains independent
RF PA paths to ensure optimal performance in both
frequency bands, while achieving a 25% PCB space
savings compared with solutions requiring two
single-band PAs. The package pinout was chosen
to enable handset manufacturers to easily route bias
to both power amplifiers and simplify control with
common mode pins. The device is manufactured on
an advanced InGaP HBT MMIC technology offering
state-of-the-art reliability, temperature stability, and
ruggedness. The AWC6323 is part of ANADIGICS’
High-Efficiency-at-Low-Power (HELP™) family of
CDMA power amplifiers, which deliver low quiescent
currents and significantly greater efficiency without
the need of an external DC-DC converter. Through
selectable bias modes, the AWC6323 achieves
optimal efficiency, specifically at low- and mid-range
power levels where the PA typically operates, thereby
dramatically increasing handset talk-time. Its built-in
voltage regulator eliminates the need for external
switches. This PA has built-in directional couplers
for each band, with a common coupler output port
CPL_OUT. The 3 mm x 5 mm x 1 mm surface mount
package incorporates matching networks optimized
for output power, efficiency and linearity in a 50 Ω
system.
VEN_CELL 1
RFIN_CELL 2
Bias Control
Voltage Regulation
CPL
14 GND
13 RFOUT_CELL
VMODE1 ₃
12 _VCC
VBATT 4
11 VCCA
VMODE2 5
10 CPLOUT
RFIN_PCS 6
CPL
9 GND
VEN_PCS 7
Bias Control
Voltage Regulation
8 RFOUT_PCS
GND at Slug (pad)
Figure 1: Block Diagram
03/2012